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41. 发明授权

US08531205B1 Programmable output buffer 有权
标题翻译：可编程输出缓冲器
公开(公告)号：US08531205B1
公开(公告)日：2013-09-10
申请号：US13363108
申请日：2012-01-31
申请人： Bonnie I. Wang , Chiakang Sung , Xiaobao Wang , Khai Nguyen , Joseph Huang
发明人： Bonnie I. Wang , Chiakang Sung , Xiaobao Wang , Khai Nguyen , Joseph Huang
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/018585 , H03K19/17744 , H03K19/17788
摘要： One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及可编程输出缓冲器，其包括第一和第二可编程可变阻抗单端驱动器电路以及第一和第二终端电路。第一终端电路耦合到由第一可编程可变阻抗单端驱动电路驱动的第一输出引脚，第二终端电路耦合到由第二可编程可变阻抗单端驱动的第二输出引脚驱动电路。第一和第二终端电路是可编程的，以提供用于差分信号的并行终端或者并联终端关断的驱动单端信号。还公开了其它实施例和特征。

42. 发明授权

US09711189B1 On-die input reference voltage with self-calibrating duty cycle correction 有权
公开(公告)号：US09711189B1
公开(公告)日：2017-07-18
申请号：US13209307
申请日：2011-08-12
申请人： Bonnie I. Wang , Chiakang Sung , Xiaobao Wang , Yan Chong , Joseph Huang , Khai Nguyen , Pradeep Nagarajan
发明人： Bonnie I. Wang , Chiakang Sung , Xiaobao Wang , Yan Chong , Joseph Huang , Khai Nguyen , Pradeep Nagarajan
IPC分类号： G11C5/14 , G11C11/4074
CPC分类号： G11C5/147 , G11C11/4074 , G11C19/00 , G11C29/021 , G11C29/028
摘要： A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.

43. 发明授权

US06681378B2 Programming mode selection with JTAG circuits 有权
标题翻译：使用JTAG电路进行编程模式选择
公开(公告)号：US06681378B2
公开(公告)日：2004-01-20
申请号：US10175980
申请日：2002-06-19
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Richard G. Cliff
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Richard G. Cliff
IPC分类号： G06F1750
CPC分类号： H03K19/1732 , G01R31/318555 , G06F11/2273 , H03K19/17744 , H03K19/17748
摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).
摘要翻译：通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

44. 发明授权

US06421812B1 Programming mode selection with JTAG circuits 失效
标题翻译：使用JTAG电路进行编程模式选择
公开(公告)号：US06421812B1
公开(公告)日：2002-07-16
申请号：US09094186
申请日：1998-06-09
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Richard G. Cliff
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Richard G. Cliff
IPC分类号： G06F1750
CPC分类号： H03K19/1732 , G01R31/318555 , G06F11/2273 , H03K19/17744 , H03K19/17748
摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).
摘要翻译：通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

45. 发明授权

US06603329B1 Systems and methods for on-chip impedance termination 有权
标题翻译：用于片上阻抗终止的系统和方法
公开(公告)号：US06603329B1
公开(公告)日：2003-08-05
申请号：US10044459
申请日：2002-01-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
IPC分类号： H03K1716
CPC分类号： H04L25/0278 , H04L25/0298
摘要： Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.
摘要翻译：提供用于片上阻抗终止的技术，其大大减少了需要在多对差分输入/输出（I / O）引脚上提供阻抗终端的外部电阻器的数量。本发明的片上阻抗终端电路可以包括放大器，反馈回路和阻抗终端电路。将参考电压提供给放大器的第一输入端。反馈回路耦合在放大器的输出端和放大器的第二输入端之间。放大器驱动其输出电压，使得第二输入端子处的电压与第一输入端子处的电压匹配。放大器的输出电压决定了阻抗终端电路的电阻。阻抗端接电路耦合在差分I / O引脚之间。

46. 发明授权

US08384460B1 Techniques for phase adjustment 有权
标题翻译：相位调整技术
公开(公告)号：US08384460B1
公开(公告)日：2013-02-26
申请号：US13420349
申请日：2012-03-14
申请人： Chiakang Sung , John Henry Bui , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang
发明人： Chiakang Sung , John Henry Bui , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang
IPC分类号： H03H11/16
CPC分类号： H03L7/0814 , H03K2005/00293
摘要： An adjustable delay circuit includes first and second transistors each having a control input coupled to an input node of the adjustable delay circuit and an output coupled to an output node of the adjustable delay circuit. The adjustable delay circuit includes a first pass gate coupled between first and second capacitors and the output node of the adjustable delay circuit. The first and the second capacitors are coupled between a node at a high voltage and a node at a low voltage. The first pass gate is operable to be controlled by a first delay control signal.
摘要翻译：可调延迟电路包括第一和第二晶体管，每个晶体管具有耦合到可调延迟电路的输入节点的控制输入和耦合到可调延迟电路的输出节点的输出。可调延迟电路包括耦合在第一和第二电容器之间的第一通过栅极和可调延迟电路的输出节点。第一和第二电容器耦合在高电压节点和低电压节点之间。第一通过门可操作以由第一延迟控制信号控制。

47. 发明授权

US08149038B1 Techniques for phase adjustment 有权
标题翻译：相位调整技术
公开(公告)号：US08149038B1
公开(公告)日：2012-04-03
申请号：US12729114
申请日：2010-03-22
申请人： Chiakang Sung , John Henry Bui , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang
发明人： Chiakang Sung , John Henry Bui , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang
IPC分类号： H03H11/16
CPC分类号： H03L7/0814 , H03K2005/00293
摘要： A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.
摘要翻译：动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。控制逻辑电路产生选择信号。控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。

48. 发明授权

US06798237B1 On-chip impedance matching circuit 有权
标题翻译：片内阻抗匹配电路
公开(公告)号：US06798237B1
公开(公告)日：2004-09-28
申请号：US10044365
申请日：2002-01-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
IPC分类号： H03K1716
CPC分类号： H04L25/0278
摘要： Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.
摘要翻译：提供具有片上阻抗匹配技术的集成电路，其大大减少耦合到集成电路的片外电阻器的数量。本发明的片上阻抗匹配电路与集成电路上的多个I / O引脚中的每一个相关联。本发明的电路可以包括具有电阻器和片上晶体管的电阻分压器。片上晶体管的电阻和电阻分压器的电压输出信号随集成电路的工艺，温度和电压而变化。阻抗匹配电路的有效通道W / L比随着电阻分压器的电压输出信号而变化，使得由过程，温度和电压变化引起的阻抗匹配电路的阻抗变化最小化。

49. 发明授权

US08610462B1 Input-output circuit and method of improving input-output signals 有权
标题翻译：输入输出电路及改善输入输出信号的方法
公开(公告)号：US08610462B1
公开(公告)日：2013-12-17
申请号：US13332730
申请日：2011-12-21
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Bonnie I. Wang
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Bonnie I. Wang
IPC分类号： H03K19/094 , H03K19/0175 , H03K3/00 , H03B1/00
CPC分类号： H03K3/356113
摘要： Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.
摘要翻译：公开了用于利用电平移位器电路来操作集成电路（IC）的电路和技术。具有输入和输出端子的电平移位器电路可操作以将从地电压到第一正电压的输入信号移动到范围从接地电压到第二正电压的输出信号。电平移位器电路还包括具有第一源极 - 漏极端子的第一汲取晶体管，第一源极 - 漏极端子可操作以接收缓冲版本的输入信号并具有耦合到输出端子的第二源极 - 漏极端子。当输入信号处于接地电压时，第一icker晶体晶体管可以接收导通第一猝发晶体管的栅极信号，并且当输入信号从接地电压转变到第一正电压时，可以将输出端拉至第一正电压。

50. 发明授权

US07973553B1 Techniques for on-chip termination 有权
标题翻译：片上终止技术
公开(公告)号：US07973553B1
公开(公告)日：2011-07-05
申请号：US12721759
申请日：2010-03-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , John Henry Bui
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , John Henry Bui
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0278
摘要： A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.
摘要翻译：电路包括第一晶体管和比较器。比较器比较参考信号和基于第一晶体管的导电状态的信号。控制电路根据比较器的输出信号产生第一控制信号。基于第一控制信号来确定第一晶体管的导通状态。算术电路基于第一控制信号和第二控制信号执行运算功能，以生成校准信号。第二晶体管在基于校准信号的电路的外部端子处提供终端阻抗。

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