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41. 发明授权

US07760123B2 Data acquisition system for photon counting and energy discriminating detectors 有权
标题翻译：用于光子计数和能量鉴别检测器的数据采集系统
公开(公告)号：US07760123B2
公开(公告)日：2010-07-20
申请号：US12198989
申请日：2008-08-27
申请人： Naresh Kesavan Rao , Brian David Yanoff , Yanfeng Du , Jianjun Guo
发明人： Naresh Kesavan Rao , Brian David Yanoff , Yanfeng Du , Jianjun Guo
IPC分类号： H03M1/12
CPC分类号： G06G7/18
摘要： A data acquisition system including a readout Application Specific Integrated Circuit (ASIC) having a plurality of channels, each channel having a time discriminating circuit and an energy discriminating circuit, wherein the ASIC is configured to receive a plurality of signals from a semiconductor radiation detector. The data acquisition system also includes a digital-to-analog converter (DAC) electrically coupled to the ASIC and configured to provide a reference signal to the ASIC used in the generation of digital outputs from the ASIC, and a controller electrically coupled to the ASIC and to the DAC, the controller configured to instruct the DAC to provide the reference signal to the ASIC.
摘要翻译：一种数据采集系统，包括具有多个通道的读出专用集成电路（ASIC），每个通道具有时间鉴别电路和能量识别电路，其中ASIC被配置为从半导体辐射检测器接收多个信号。数据采集系统还包括电耦合到ASIC的数模转换器（DAC），并被配置为向ASIC中产生数字输出使用的ASIC提供参考信号，以及电耦合到ASIC的控制器并且所述控制器被配置为指示所述DAC向所述ASIC提供所述参考信号。

42. 发明授权

US07741611B2 Radiation detector power management for portable/handheld applications 有权
标题翻译：用于便携式/手持应用的辐射检测器电源管理
公开(公告)号：US07741611B2
公开(公告)日：2010-06-22
申请号：US12220230
申请日：2008-07-23
申请人： Yanfeng Du , Naresh Kesavan Rao , Brian David Yanoff , Wen Li
发明人： Yanfeng Du , Naresh Kesavan Rao , Brian David Yanoff , Wen Li
IPC分类号： G01T1/24
CPC分类号： G01T1/244 , G01T7/00
摘要： A radiation detector includes at least one multiple channel pixelated detector driven via a plurality of pixelated anode electrodes and at least one planar cathode electrode. Each detector is configured to reduce the number of active pixelated anode electrodes until a rate of events detected via at least one corresponding planar cathode electrode exceeds a preset threshold above a background count rate within a predetermined time period.
摘要翻译：辐射检测器包括经由多个像素化阳极电极和至少一个平面阴极电极驱动的至少一个多通道像素化检测器。每个检测器被配置为减少活性像素化阳极电极的数量，直到经由至少一个对应的平面阴极电极检测到的事件的速率超过在预定时间段内的背景计数率以上的预设阈值。

43. 发明申请

US20080001095A1 ADAPTIVE IMAGING SYSTEM 审中-公开
标题翻译：自适应成像系统
公开(公告)号：US20080001095A1
公开(公告)日：2008-01-03
申请号：US11427534
申请日：2006-06-29
申请人： Oliver Richard Astley , John Eric Tkaczyk , Naresh Kesavan Rao , James Walter LeBlanc , Wen Li , Yanfeng Du
发明人： Oliver Richard Astley , John Eric Tkaczyk , Naresh Kesavan Rao , James Walter LeBlanc , Wen Li , Yanfeng Du
IPC分类号： G01T1/16
CPC分类号： G01T1/17 , G01T1/2985
摘要： An adaptive imaging system includes a detector receiving energy transmitted through a target and generating electrical charge pulses at a pulse rate indicative of an intensity of received energy. The system also includes a switch for selectively coupling the charge pulses from one or more pixel elements of the detector to a charge pulse counter for counting the charge pulses and a charge pulse integrator for integrating the charge pulses. In addition, the system includes a prediction module for predicting a charge pulse rate expected to be produced by the detector and for operating the switch to selectively couple the charge pulses to the counter and the integrator responsive to a predicted charge pulse rate.
摘要翻译：自适应成像系统包括检测器，其接收通过目标传输的能量，并以指示接收能量的强度的脉冲速率产生电荷脉冲。该系统还包括用于选择性地将来自检测器的一个或多个像素元件的充电脉冲耦合到用于计数充电脉冲的充电脉冲计数器和用于积分充电脉冲的充电脉冲积分器的开关。此外，该系统包括预测模块，用于预测由检测器产生的充电脉冲速率，并且用于操作开关以根据预测的充电脉冲速率选择性地将充电脉冲耦合到计数器和积分器。

44. 发明授权

US07164379B1 Pipeline analog to digital converter 有权
标题翻译：管道模数转换器
公开(公告)号：US07164379B1
公开(公告)日：2007-01-16
申请号：US11289934
申请日：2005-11-30
申请人： Naresh Kesavan Rao
发明人： Naresh Kesavan Rao
IPC分类号： H03M1/38
CPC分类号： H03M1/52 , H03M1/141
摘要： An analog to digital conversion circuit includes a first circuit (10) for receiving an analog signal (16) applied to an input (e.g., 26) of the first circuit via a connection to an analog source (e.g., 18) and generating a first residue (58) of the analog signal at an output (e.g., 32). The first circuit may be selectively configurable in a first mode for integrating the analog signal to generate an integrated analog signal and configurable in a second mode for disconnecting the first circuit from the analog source while folding the integrated analog signal to generate the first residue. The analog to digital conversion circuit also includes a second circuit (60) coupled to the output of the first circuit for resolving the first residue provided by the first circuit and for generating a further resolved second residue (98).
摘要翻译：模数转换电路包括：第一电路（10），用于经由与模拟源（例如18）的连接来接收施加到第一电路的输入（例如26）的模拟信号（16），并产生第一在输出端（例如32）处的模拟信号的残差（58）。第一电路可以选择性地配置在第一模式中，用于对模拟信号进行积分以产生集成的模拟信号，并且可在第二模式中配置，以便在折叠集成模拟信号以产生第一残差的同时将第一电路与模拟源断开连接。模数转换电路还包括耦合到第一电路的输出的第二电路（60），用于解析由第一电路提供的第一残余物并产生另外的分辨的第二残留物（98）。

45. 发明授权

US07095354B2 Very linear wide-range pipelined charge-to-digital converter 有权
标题翻译：非常线性的大范围流水线电荷数字转换器
公开(公告)号：US07095354B2
公开(公告)日：2006-08-22
申请号：US11203493
申请日：2005-08-12
申请人： Daniel David Harrison , Naresh Kesavan Rao , Shobhana Mani , Naveen Stephan Chandra , Oliver Richard Astley , Donald Thomas McGrath
发明人： Daniel David Harrison , Naresh Kesavan Rao , Shobhana Mani , Naveen Stephan Chandra , Oliver Richard Astley , Donald Thomas McGrath
IPC分类号： H03M1/36
CPC分类号： H03M1/0609 , H03M1/1215 , H03M1/141 , H03M1/60
摘要： A multi-channel analog to digital conversion circuit and methods thereon are provided. The multi-channel analog to digital conversion cirucit comprises a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter wherein analog residue is processed by subsequent analog to digital converter stages. Each stage of respective linearized channels is configured for calculating gain and offset for each stage in the channel and such gain and offset is used in subsequent integration periods.
摘要翻译：提供了多通道模数转换电路及其方法。多通道模数转换电路包括多个线性化通道，其中每个通道包括多级流水线电荷数字转换器和在多级转换器的每个级内的积分电容器，其中模拟残余物由后续处理模数转换器级。各个线性化信道的每个级被配置为用于计算信道中每个级的增益和偏移，并且在随后的积分周期中使用这种增益和偏移。

46. 发明授权

US07053806B1 System and method for calibration of autoranging architectures 失效
标题翻译：自动量程架构校准的系统和方法
公开(公告)号：US07053806B1
公开(公告)日：2006-05-30
申请号：US11094903
申请日：2005-03-31
申请人： Naresh Kesavan Rao , Jianjun Guo
发明人： Naresh Kesavan Rao , Jianjun Guo
IPC分类号： H03M1/10
CPC分类号： H03M1/1028 , H03M1/187 , H03M1/58
摘要： A method for calibrating a segmented analog to digital signal conversion system is provided. The method includes segmenting a desired relationship between DAC output values and desired ADC input values into a plurality of segments. Each of the plurality of segments includes an offset value and a gain value. The method also includes computing the offset value and an offset coefficient for each of the plurality of segments, computing the gain value and an gain coefficient for each of the plurality of segments, and storing the offset value and the gain value for each of the plurality of segments in a memory unit for reference in converting an analog signal to a digital signal based upon the gain value and offset value.
摘要翻译：提供了一种用于校准分段的模数转换系统的方法。该方法包括将DAC输出值和期望的ADC输入值之间的期望关系分割成多个段。多个段中的每一个包括偏移值和增益值。该方法还包括计算多个段中的每个段的偏移值和偏移系数，计算多个段中的每一个的增益值和增益系数，以及存储多个段中的每一个的偏移值和增益值的存储器单元中的段，用于基于增益值和偏移值将模拟信号转换为数字信号。

47. 发明授权

US06448713B1 Sensing and control for dimmable electronic ballast 失效
标题翻译：可调光电子镇流器的感应和控制
公开(公告)号：US06448713B1
公开(公告)日：2002-09-10
申请号：US09731000
申请日：2000-12-07
申请人： Thomas Farkas , Naresh Kesavan Rao
发明人： Thomas Farkas , Naresh Kesavan Rao
IPC分类号： H05B3702
CPC分类号： H05B41/3924 , H05B41/3921
摘要： A sensing circuit for a triac dimmable gas discharge lamp ballast uses the duty cycle of the output waveform of a conventional triac dimmer as the parameter representing a set point for controlling the degree of clamping applied to the ballast circuit, and thus the amount of light produced by a fluorescent lamp. The sensing circuit may include a comparator that receives a rectified output waveform of a triac dimmer and produces output pulses corresponding in width to the duty cycle of the waveform, and a capacitor averaging the values of the pulses produced by the comparator to produce a set point signal representing a dimming level of the lamp. A triac dimmable ballast circuit using this sensing circuit has reduced sensitivity to line voltage and a wide mechanical range over which the light level of the fluorescent lamp is controlled by the user. The sensing circuit also enables a preheat timing circuit that eliminates the timing capacitor of prior art preheating circuits. A gas discharge lamp ballast and a method for its operation are also disclosed.
摘要翻译：用于三端双向可控硅可调光气体放电灯镇流器的感测电路使用常规三端双向可控硅调光器的输出波形的占空比作为表示用于控制施加到镇流器电路的钳位程度的设定点的参数，并且因此产生的光量通过荧光灯。感测电路可以包括比较器，其接收三端双向可控硅调光器的整流输出波形，并产生宽度对应于波形的占空比的输出脉冲，以及对由比较器产生的脉冲的值进行平均以产生设定点表示灯的调光电平的信号。使用该感测电路的三端双向可控硅可调光镇流器电路降低了对线路电压的敏感性以及荧光灯的光级由用户控制的宽的机械范围。感测电路还使得能够消除现有技术的预热电路的定时电容器的预热定时电路。还公开了一种气体放电灯镇流器及其操作方法。

48. 发明授权

US06366231B1 Integrate and fold analog-to-digital converter with saturation prevention 失效
标题翻译：集成和折叠具有饱和度预防的模数转换器
公开(公告)号：US06366231B1
公开(公告)日：2002-04-02
申请号：US09546623
申请日：2000-04-10
申请人： Naresh Kesavan Rao , Daniel David Harrison , Donald Thomas McGrath , Jerome Johnson Tiemann
发明人： Naresh Kesavan Rao , Daniel David Harrison , Donald Thomas McGrath , Jerome Johnson Tiemann
IPC分类号： H03M150
CPC分类号： H03M1/141 , H03M1/1215 , H03M1/60
摘要： An analog to digital conversion circuit for converting an analog input signal into a plurality of binary output bits includes an operational amplifier and an integrating capacitor for storing a charge proportional to the integral of the input signal. A charge subtracting circuit removes a first predetermined charge from the integrating capacitor when an output charge of the operational amplifier is substantially equal to a second predetermined charge. The first predetermined charge level is removed from the integrating capacitor a number of times. The removal of the first predetermined charge from the integrating capacitor allows the integral of the analog input signal to be larger than a maximum charge capable of being stored by the integrating capacitor. A digital logic circuit tracks the number of times that the first predetermined charge is removed from the integrating capacitor by the charge subtracting circuit, and the digital logic circuit provides at least one bit of the plurality of binary output bits. A residue quantizing circuit determines a residual charge in the integrating capacitor and provides at least one additional bit of the plurality of binary output bits corresponding to the residual charge. The residual charge is substantially equal to a stored charge in the integrating capacitor after the first predetermined charge has been removed the number of times.
摘要翻译：用于将模拟输入信号转换成多个二进制输出位的模数转换电路包括运算放大器和用于存储与输入信号的积分成比例的电荷的积分电容器。当运算放大器的输出电荷基本上等于第二预定电荷时，电荷减去电路从积分电容器去除第一预定电荷。第一预定电荷电平从积分电容器中多次去除。从积分电容器去除第一预定电荷允许模拟输入信号的积分大于能够由积分电容器存储的最大电荷。数字逻辑电路跟踪由电荷减法电路从积分电容器去除第一预定电荷的次数，数字逻辑电路提供多个二进制输出位的至少一位。残余量化电路确定积分电容器中的残余电荷，并提供与剩余电荷相对应的多个二进制输出位中的至少一个附加位。残余电荷基本上等于在第一预定电荷已被去除次数之后积分电容器中的存储电荷。

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