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    • 41. 发明授权
    • Transceiver circuit and method of transmitting a signal which uses an
output transistor to send data and assist in pulling up a bus
    • 收发器电路和发送信号的方法,该信号使用输出晶体管发送数据并协助提升总线
    • US5652528A
    • 1997-07-29
    • US560368
    • 1995-11-17
    • Masaharu KimuraToshiro Takahashi
    • Masaharu KimuraToshiro Takahashi
    • H03K19/017H03K19/0185
    • H03K19/018507H03K19/01721
    • A semiconductor integrated circuit device having an input/output circuit for inputting and outputting data having a GTL level includes a pull-down output MOSFET (Q1) and a pull-up output MOSFET (Q2) both electrically connected to an input/output terminal and a gate drive signal generating circuit (DPG) electrically coupled to the gate of the pull-up output MOSFET (Q2). Upon data transmission, the gate drive signal generating circuit (DPG) controls the operation of the output MOSFET (Q2) so that the output MOSFETs (Q1 and Q2) are contemporarily brought into an ON or OFF state according to data to be transmitted. On the other hand, upon data reception, the gate drive signal generating circuit (DPG) forms a control pulse for temporarily turning ON one of the output MOSFETS (Q2) immediately after high-level data has been received, and supplies it to a gate terminal of the output MOSFET (Q2).
    • 具有用于输入和输出具有GTL电平的数据的输入/输出电路的半导体集成电路装置包括电连接到输入/输出端子的下拉输出MOSFET(Q1)和上拉输出MOSFET(Q2),以及 电耦合到上拉输出MOSFET(Q2)的栅极的栅极驱动信号发生电路(DPG)。 在数据传输时,栅极驱动信号发生电路(DPG)控制输出MOSFET(Q2)的工作,使得输出MOSFET(Q1和Q2)根据要传输的数据同时进入ON或OFF状态。 另一方面,在数据接收时,栅极驱动信号生成电路(DPG)形成用于在接收到高电平数据之后立即接通输出MOSFET(Q2)中的一个的控制脉冲,并将其提供给门 端子(Q2)。
    • 42. 发明授权
    • Substrate for magnetic recording medium and process of producing the same
    • 磁记录介质用基板及其制造方法
    • US5277960A
    • 1994-01-11
    • US872167
    • 1992-04-22
    • Noboru TsuyaToshiro Takahashi
    • Noboru TsuyaToshiro Takahashi
    • G11B5/66G11B5/73G11B5/82G11B5/84B32B3/30B32B15/08
    • G11B5/7315G11B5/7325G11B5/8404Y10S428/90Y10T428/24612Y10T428/31678
    • The first invention provides a substrate for a magnetic recording medium, which is prepared by forming a macro-concavo-convex pattern for improving CSS properties and a micro-concavo-convex pattern for improving magnetic properties on the surface, thereby preventing the degradation of the CSS properties brought by the enhancement in friction coefficient and the increase in the area of a protective layer of the medium in contact with a magnetic head, caused by the wearing of the protective layer of the medium.The second invention provides a process of producing a substrate for a magnetic recording medium, which forms the above macro-concavo-convex pattern and micro-concavo-convex pattern in a uniform distribution at the same time.The first invention utilizes, as the texture, protrusions 13P and 15P different in length from the substrate surface, the protrusions being prepared by packing at least two kinds of materials 13 and 15 differing in etching rate into alumite pores 14A and 14B, polishing and then etching.The second process invention comprises the steps of packing the first material into alumite pores of an aluminum alloy by means of electrolytic deposition, packing the second material having an etching rate different from that of the first material by means of dipping method, polishing the resultant surface and etching the polished surface so as to make the respective protrusion lengths of the first and the second materials within the predetermined range.
    • 第一发明提供了一种用于磁记录介质的基板,其通过形成用于改善CSS性质的宏观凹凸图案和用于改善表面上的磁性能的微凹凸图案来制备,从而防止了 通过介质的保护层的磨损而引起的摩擦系数的增强和与磁头接触的介质的保护层的面积增加引起的CSS性质。 第二发明提供了一种制造用于磁记录介质的衬底的方法,其同时形成均匀分布的上述宏观凹凸图案和微凹凸图案。 第一发明利用了与基板表面不同长度的突起13P和15P作为纹理,通过将蚀刻速率不同的至少两种材料13和15填充到耐氧化铝孔14A和14B中来进行抛光,然后抛光 蚀刻。 第二工艺方法包括以下步骤:通过电解沉积将第一种材料包装到铝合金的防氧化铝孔中,通过浸渍法将具有不同于第一种材料的蚀刻速率的第二种材料包装, 并且蚀刻抛光表面以使第一和第二材料的相应突出长度在预定范围内。
    • 43. 发明授权
    • Pattern synchronizing circuit
    • 图案同步电路
    • US5210754A
    • 1993-05-11
    • US710522
    • 1991-06-04
    • Toshiro TakahashiTakayuki NakajimaTetsuo SotomeNoboru Akiyama
    • Toshiro TakahashiTakayuki NakajimaTetsuo SotomeNoboru Akiyama
    • H04L1/00H04J3/06H04L7/00
    • H04J3/0608
    • An Nth one of N parallel sequences of low-speed data demultiplexed by a demultiplexer from high-speed input data in synchronization with a high-speed clock is compared by N comparators with N parallel sequences of reference patterns. The N parallel sequences of reference patterns are each generated in synchronization with a frequency divided clock obtained by frequency dividing the high-speed clock into 1/N. When any of the comparators provides a disagreement output at least once, one clock pulse is eliminated by a post-clock eliminating circuit from the divided clock so that the N sequences of reference patterns are each delayed by one bit. When a counter detects that any one of the comparators does not provide the disagreement signal for n consecutive bits, the sequence of reference patterns corresponding to this comparator and the Nth sequence of low-speed data are in synchronization with each other. Clock pulses of the number corresponding to the line position of the synchronized sequence of reference patterns are eliminated by a pre-clock eliminating circuit from the high-speed clock which is applied to the demultiplexer. By this, line positions of the N parallel sequences of low-speed data are sequentially shifted so that the Nth sequence of low-speed data assumes the same line position as that of the synchronized reference pattern, and as a result, the N parallel sequences of low-speed data are synchronized with the N parallel sequences of reference patterns, respectively.
    • 47. 发明授权
    • Average frequency measuring apparatus
    • 平均频率测量仪
    • US4468614A
    • 1984-08-28
    • US378268
    • 1982-05-14
    • Toshiro TakahashiShoji Niki
    • Toshiro TakahashiShoji Niki
    • G01R23/02G01R23/10
    • G01R23/02G01R23/10
    • An average frequency measuring apparatus in which auxiliary gate signals are converted into synchronized gate signals synchronized with either input signals or clock signals; first and second gates are opened by the synchronized gate signals; the input signals and the clock signals having passed through the first and second gates are counted by first and second counters, respectively; and the frequency of the input signals is calculated from the count values of the first and second counters for a plurality of occurrences of the synchronized gate signal. A third counter is provided for counting the number of the synchronized gate signals, and a minimum counting time is calculated by calculating means from the count values of the third and second counters and the set measurement accuracy. When it is detected from the count value of the second or third counter that the actual counting time has been exceeded, measurement is stopped, thereby obtaining measured results of accuracy at least higher than the set measurement accuracy.
    • 平均频率测量装置,其中辅助门信号被转换成与输入信号或时钟信号同步的同步门信号; 第一和第二门由同步的门信号打开; 已经通过第一和第二门的输入信号和时钟信号分别由第一和第二计数器计数; 并且对于多个同步的门信号的出现,从第一和第二计数器的计数值计算输入信号的频率。 提供第三计数器用于对同步的门信号的数量进行计数,并且通过从第三和第二计数器的计数值和设定的测量精度计算装置来计算最小计数时间。 当从第二或第三计数器的计数值检测到实际计数时间已被超过时,测量停止,从而获得至少高于设定的测量精度的测量结果。