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41. 发明授权

US07522692B2 Isolator and a modem device using the isolator 失效
标题翻译：隔离器和使用隔离器的调制解调器设备
公开(公告)号：US07522692B2
公开(公告)日：2009-04-21
申请号：US11714856
申请日：2007-03-07
申请人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
发明人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
IPC分类号： H04L23/00 , H04B1/38 , H01L29/00
CPC分类号： H04L25/0266 , H01L2924/0002 , H04L25/0268 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L27/0002 , H04M11/06 , H01L2924/00
摘要： A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.
摘要翻译：提供一种通信系统，包括收发机和应用控制器，用于通过收发信机发送和接收信号。绝缘和分离收发器和应用控制器的隔离器包括在基板上彼此绝缘的初级和次级侧电路和用于在初级侧和第二侧之间传递信号的电容绝缘装置，同时将初级侧电路与次级侧隔离电路。

42. 发明申请

US20080303175A1 Electronic circuit package 失效
标题翻译：电子电路封装
公开(公告)号：US20080303175A1
公开(公告)日：2008-12-11
申请号：US12222329
申请日：2008-08-07
申请人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
发明人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
IPC分类号： H01L23/52
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor
摘要翻译：一种电子设备，其包括布线基板和布线基板上形成的多个半导体裸芯片。半导体裸芯片包括用于处理数据的处理器和具有用于检测处理器的故障的检查功能的电路

43. 发明授权

US07456603B2 Phase detection circuit, resolver/digital converter using the circuit, and control system using the converter 有权
标题翻译：相位检测电路，采用电路的解算器/数字转换器，以及使用转换器的控制系统
公开(公告)号：US07456603B2
公开(公告)日：2008-11-25
申请号：US11488158
申请日：2006-07-18
申请人： Nobuyasu Kanekawa , Shoji Sasaki , Katsuya Oyama , Tomonobu Koseki
发明人： Nobuyasu Kanekawa , Shoji Sasaki , Katsuya Oyama , Tomonobu Koseki
IPC分类号： H02P23/00
CPC分类号： H03M1/485 , G01D5/2073
摘要： A small-sized and low-cost phase detection circuit which has improved noise immunity. The phase detection circuit comprises a multiplier for multiplying an input signal by a reference signal and outputting a first signal, an integration circuit for integrating the first signal and outputting a second signal, a phase estimation circuit for estimating phase information based on the second signal, and a reference signal generation circuit for generating the reference signal based on the estimated phase information. Since the phase is detected based on information representing an entire waveform, the influence of local noise can be diluted and noise immunity can be improved.
摘要翻译：具有改进的抗噪声性能的小型和低成本的相位检测电路。相位检测电路包括用于将输入信号乘以参考信号并输出第一信号的乘法器，用于积分第一信号并输出第二信号的积分电路，用于基于第二信号估计相位信息的相位估计电路，以及参考信号生成电路，用于基于估计的相位信息产生参考信号。由于基于表示整个波形的信息来检测相位，所以能够稀释局部噪声的影响，能够提高抗噪声性。

44. 发明申请

US20080116886A1 Displacement Sensor Using GMR Elements, Angle Sensor Using GMR Elements, And Semiconductor Device Used For Them 有权
标题翻译：使用GMR元件的位移传感器，使用GMR元件的角度传感器及其半导体器件
公开(公告)号：US20080116886A1
公开(公告)日：2008-05-22
申请号：US11926583
申请日：2007-10-29
申请人： Masamichi Yamada , Nobuyasu Kanekawa , Kenji Nakabayashi
发明人： Masamichi Yamada , Nobuyasu Kanekawa , Kenji Nakabayashi
IPC分类号： G01B7/30 , H01L43/08
CPC分类号： G01D5/145
摘要： A highly accurate displacement sensor using GMR elements for detecting a displacement of a physical quantity such as angle is to be provided wherein a waveform distortion of output voltage is diminished.There are installed at least two Wheatstone bridge circuits having a predetermined angular offset and each comprising a plurality of GMR elements, the GMR elements each having a fixed magnetic layer set to a predetermined magnetization direction. An AC power supply is use as a power supply of the Wheatstone bridge circuits and a displacement of a physical quantity such as a rotational angle is detected on the basis of AC-modulated outputs from the Wheatstone bridge circuits.An anisotropic self-bias effect of a free magnetic layer in each GMR element can be diminished and hence it is possible to remedy a waveform distortion of an output signal based on the anisotropic self-bias effect of the free magnetic layer.
摘要翻译：提供一种使用GMR元件检测诸如角度的物理量的位移的高精度位移传感器，其中输出电压的波形失真减小。安装有至少两个具有预定角度偏移的惠斯通电桥电路，每个包含多个GMR元件，每个具有固定的磁性层设置为预定的磁化方向的GMR元件。使用交流电源作为惠斯登电桥电路的电源，并且基于惠斯通电桥电路的交流调制输出来检测物理量（例如旋转角度）的位移。可以减少每个GMR元件中的自由磁性层的各向异性自偏置效应，因此可以基于自由磁性层的各向异性自偏置效应来补偿输出信号的波形失真。

45. 发明申请

US20070029955A1 Phase detection circuit, resolver/digital converter using the circuit, and control system using the converter 有权
标题翻译：相位检测电路，采用电路的解算器/数字转换器，以及使用转换器的控制系统
公开(公告)号：US20070029955A1
公开(公告)日：2007-02-08
申请号：US11488158
申请日：2006-07-18
申请人： Nobuyasu Kanekawa , Shoji Sasaki , Katsuya Oyama , Tomonobu Koseki
发明人： Nobuyasu Kanekawa , Shoji Sasaki , Katsuya Oyama , Tomonobu Koseki
IPC分类号： H02P7/32
CPC分类号： H03M1/485 , G01D5/2073
摘要： A small-sized and low-cost phase detection circuit which has improved noise immunity. The phase detection circuit comprises a multiplier for multiplying an input signal by a reference signal and outputting a first signal, an integration circuit for integrating the first signal and outputting a second signal, a phase estimation circuit for estimating phase information based on the second signal, and a reference signal generation circuit for generating the reference signal based on the estimated phase information. Since the phase is detected based on information representing an entire waveform, the influence of local noise can be diluted and noise immunity can be improved.
摘要翻译：具有改进的抗噪声性能的小型和低成本的相位检测电路。相位检测电路包括用于将输入信号乘以参考信号并输出第一信号的乘法器，用于积分第一信号并输出第二信号的积分电路，用于基于第二信号估计相位信息的相位估计电路，以及参考信号生成电路，用于基于估计的相位信息产生参考信号。由于基于表示整个波形的信息来检测相位，所以能够稀释局部噪声的影响，能够提高抗噪声性。

46. 发明授权

US06972700B2 Resolver/digital converter and control apparatus using the same 有权
标题翻译：转换器/数字转换器及使用其的控制装置
公开(公告)号：US06972700B2
公开(公告)日：2005-12-06
申请号：US11043639
申请日：2005-01-27
申请人： Nobuyasu Kanekawa , Shoji Sasaki , Katsuya Oyama , Tomonobu Koseki
发明人： Nobuyasu Kanekawa , Shoji Sasaki , Katsuya Oyama , Tomonobu Koseki
IPC分类号： G01D5/244 , B60T8/88 , B60T17/18 , B62D5/04 , G01D5/20 , G05B9/02 , G05D3/12 , H03M1/10 , H03M1/64 , H03M1/00 , G05B1/06
CPC分类号： B60T8/885 , B60T2270/402 , B62D5/0481 , G01D5/2073 , G05B9/02 , H03M1/1076 , H03M1/645
摘要： This resolver/digital converter has a resolver, a resolver/digital converting portion and an exciting signal generator. The exciting signal generated from the exciting signal generator is supplied to the resolver, and the resolver signals produced from the resolver are supplied to the resolver/digital converter. This resolver/digital converter further has a conversion trigger generator that generates a conversion trigger signal on the basis of the exciting signal generated from the exciting signal generator, an A/D converter that converts the resolver signals produced from the resolver to digital values in response to the conversion trigger signal generated from the conversion trigger generator, and computing means that detects the failure status on the basis of the digital values produced from the A/D converter.
摘要翻译：该解算器/数字转换器具有分解器，分解器/数字转换部分和激励信号发生器。从激励信号发生器产生的激励信号被提供给解算器，并且从分解器产生的解算器信号被提供给解算器/数字转换器。该解算器/数字转换器还具有转换触发发生器，其基于从激励信号发生器产生的激励信号产生转换触发信号，A / D转换器将从分解器产生的分解器信号转换为数字值涉及从转换触发发生器产生的转换触发信号，以及基于从A / D转换器产生的数字值来检测故障状态的计算装置。

47. 发明授权

US06476750B1 Over-sampling A/D, D/A converter 失效
标题翻译：过采样A / D，D / A转换器
公开(公告)号：US06476750B1
公开(公告)日：2002-11-05
申请号：US09485349
申请日：2000-02-09
申请人： Nobuyasu Kanekawa , Yasuyuki Kojima , Seigou Yukutake , Minehiro Nemoto , Kazuhisa Takami , Takayuki Iwasaki , Yusuke Takeuchi , Katsuhiro Furukawa
发明人： Nobuyasu Kanekawa , Yasuyuki Kojima , Seigou Yukutake , Minehiro Nemoto , Kazuhisa Takami , Takayuki Iwasaki , Yusuke Takeuchi , Katsuhiro Furukawa
IPC分类号： H03M112
CPC分类号： H03M3/392 , H03M3/498
摘要： The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.
摘要翻译：提供过采样A / D和D / A转换器的硬件，哪个硬件能够使用任何一种软件进行操作：一种对应于过采样率固定的第一种方法，另一种对应到过采样比是可变的第二种方法。写入伪分频比寄存器11的值N3和写在伪过采样比寄存器21上的值N4由转换电路12通过用户接口转换成分频比N1 转换后的结果写入分频比寄存器10。

48. 发明授权

US06407432B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06407432B1
公开(公告)日：2002-06-18
申请号：US09446846
申请日：1999-12-29
申请人： Minehiro Nemoto , Yasuyuki Kojima , Nobuyasu Kanekawa , Seigou Yukutake , Katsuhiro Furukawa
发明人： Minehiro Nemoto , Yasuyuki Kojima , Nobuyasu Kanekawa , Seigou Yukutake , Katsuhiro Furukawa
IPC分类号： H01L2701
CPC分类号： H01L21/76264 , H01L21/7624 , H01L21/76283 , H01L21/76291 , H01L23/49541 , H01L23/642 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/48464 , H01L2224/49175 , H01L2924/00014 , H01L2924/01013 , H01L2924/01079 , H01L2924/10161 , H01L2924/12043 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2224/85399
摘要： A small sized semiconductor device having a high insulating performance between a primary side circuit and a secondary side circuit is realized. A circuit region 2, plural first and second terminal electrodes 5 connected to the circuit region 3, and an insulation-separation region 4 for separating electrically the first terminal electrodes from the second terminal electrodes, and for transmitting signals between the first and the second terminal electrodes are formed onto a semiconductor chip 1, and the insulation-separation region 4 is provided between the first and second terminal electrodes. The interval between the first and the second terminal electrodes on the same semiconductor chip can be separated with high insulating performance.
摘要翻译：实现了在初级侧电路和次级侧电路之间具有高绝缘性能的小尺寸半导体器件。电路区域2，连接到电路区域3的多个第一和第二端子电极5以及用于将第一端子电极与第二端子电极分离并用于在第一和第二端子之间传输信号的绝缘分离区域4 电极形成在半导体芯片1上，并且绝缘分离区域4设置在第一和第二端子电极之间。相同半导体芯片上的第一和第二端子电极之间的间隔可以以高绝缘性能分离。

49. 发明授权

US6092217A Logic circuit having error detection function, redundant resource management method and fault tolerant system using it 失效
标题翻译：具有错误检测功能的逻辑电路，冗余资源管理方法和使用它的容错系统
公开(公告)号：US6092217A
公开(公告)日：2000-07-18
申请号：US962879
申请日：1997-11-03
申请人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
发明人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
IPC分类号： G05B9/03 , G06F11/00 , G06F11/08 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/267 , G06F7/02 , H04L1/00
CPC分类号： G06F11/0763 , G05B9/03 , G06F11/085 , G06F11/1695 , G06F11/188 , G06F11/2023 , G06F11/2035 , G06F11/2215 , G06F11/008 , G06F11/0796 , G06F11/18
摘要： A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.
摘要翻译：对于高度可靠的系统配置有用的自检电路包括具有错误检测功能的逻辑电路。对于用于输出至少双工的多个信号的功能块，逻辑电路比较功能块的输出信号，并且基于比较的结果来检测错误。逻辑电路包括合成装置，用于将预先分配的固有波形与功能块的各个输出信号叠加到一个功能块的输出信号上。固有波形是由正交波形发生器电路产生的正交波形。逻辑电路还包括比较装置，用于将合成装置的信号输出与另一功能块的信号输出进行比较，以检测误差。包括功能块的整个电路仅在存在两个输出信号固有的波形时才被判定为正常。

50. 发明授权

US5802266A Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it 失效
标题翻译：具有错误检测功能的逻辑电路，冗余资源管理方法和使用它的容错系统
公开(公告)号：US5802266A
公开(公告)日：1998-09-01
申请号：US323094
申请日：1994-10-14
申请人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
发明人： Nobuyasu Kanekawa , Shoji Suzuki , Yoshimichi Sato , Korefumi Tashiro , Keisuke Bekki , Hiroshi Sato , Makoto Nohmi , Shinya Ohtsuji
IPC分类号： G05B9/03 , G05B13/02 , G06F11/00 , G06F11/08 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/267 , G06F17/50 , H03K19/007 , G06F7/02 , H04L1/00
CPC分类号： G05B9/03 , G06F11/0763 , G06F11/085 , G06F11/1608 , G06F11/1695 , G06F11/188 , G06F11/2215 , G06F11/0796
摘要： A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing circuitry provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also compares the output signals having the superimposed inherent waveforms with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.
摘要翻译：对于高度可靠的系统配置有用的自检电路包括具有错误检测功能的逻辑电路。对于用于输出至少双工的多个信号的功能块，逻辑电路比较功能块的输出信号，并且基于比较的结果来检测错误。逻辑电路包括合成电路，用于将预先分配的固有波形叠加到功能块的各个输出信号到功能块之一的输出信号上。固有波形是由正交波形发生器电路产生的正交波形。逻辑电路还将具有叠加的固有波形的输出信号与另一功能块的信号输出进行比较，以检测错误。包括功能块的整个电路仅在存在两个输出信号固有的波形时才被判定为正常。

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