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41. 发明授权

US4677592A Dynamic RAM 失效
标题翻译：动态RAM
公开(公告)号：US4677592A
公开(公告)日：1987-06-30
申请号：US739171
申请日：1985-05-30
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40615 , G11C11/406
摘要： In a dynamic RAM, the refreshing operation is performed during one cycle of the read or write operation. A switch circuit selects either a row address signal output from address input circuit or a refresh row address signal output from a refresh circuit. By controlling the switch circuit by a switch selector, the refresh is performed during the operation delay time of the address input circuit or an input/output circuit for inputting and outputting data.
摘要翻译：在动态RAM中，刷新操作在读取或写入操作的一个周期期间执行。开关电路选择从地址输入电路输出的行地址信号或从刷新电路输出的刷新行地址信号。通过开关选择器控制开关电路，在地址输入电路的操作延迟时间或输入和输出数据的输入/输出电路中进行刷新。

42. 发明授权

US4555778A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4555778A
公开(公告)日：1985-11-26
申请号：US636220
申请日：1984-07-31
申请人： Takayasu Sakurai
发明人： Takayasu Sakurai
IPC分类号： G11C11/41 , G11C7/10 , G11C8/12 , G11C8/14 , G11C11/413 , G11C8/00
CPC分类号： G11C7/10 , G11C8/12 , G11C8/14
摘要： Disclosed is a semiconductor memory device in which a group of memory cells consists of a plurality of memory sections, each memory section is provided with a first data line, and a second data line is provided for connecting together the first data lines.
摘要翻译：公开了一种半导体存储器件，其中一组存储器单元由多个存储器部分组成，每个存储器部分设置有第一数据线，并且第二数据线被提供用于将第一数据线连接在一起。

43. 发明授权

US09000751B2 Voltage detecting circuit 有权
标题翻译：电压检测电路
公开(公告)号：US09000751B2
公开(公告)日：2015-04-07
申请号：US13396235
申请日：2012-02-14
申请人： Po-Hung Chen , Makoto Takamiya , Takayasu Sakurai
发明人： Po-Hung Chen , Makoto Takamiya , Takayasu Sakurai
IPC分类号： G01R1/30 , G01R19/165 , G01F3/20
CPC分类号： G01R19/16519 , G01F3/20
摘要： In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.
摘要翻译：在电压检测电路中，晶体管被配置为P型MOSFET，并且包括与输入端连接的源极，与接地电压端子连接的栅极和与输出端子连接的漏极。晶体管被配置为P型MOSFET，并且包括与输出端连接的栅极和源极以及与接地端子连接的漏极。调节晶体管的栅极宽度和栅极长度，并调整晶体管的栅极宽度和栅极长度，使得在晶体管的源极和漏极之间流动的源极 - 漏极电流变得等于在源极和漏极之间流动的源极 - 漏极电流当施加到输入端子的电压被设置为预置触发电压时，晶体管。该配置通过简单的配置实现了输入电压超过触发电压的检测。

44. 发明申请

US20140104952A1 INTEGRATED CIRCUIT DEVICE 有权
标题翻译：集成电路设备
公开(公告)号：US20140104952A1
公开(公告)日：2014-04-17
申请号：US14118464
申请日：2012-05-11
申请人： Ken Takeuchi , Teruyoshi Hatanaka , Koichi Ishida , Tadashi Yasufuku , Makoto Takamiya , Takayasu Sakurai
发明人： Ken Takeuchi , Teruyoshi Hatanaka , Koichi Ishida , Tadashi Yasufuku , Makoto Takamiya , Takayasu Sakurai
IPC分类号： H02M3/155 , G11C16/30
CPC分类号： H02M3/155 , G11C16/06 , G11C16/26 , G11C16/30 , G11C16/3418 , H02M3/158 , H02M2001/007
摘要： A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.
摘要翻译：升压电路被配置为：响应于从闪速存储器读取数据的读取请求，当由电压检测电路检测到的输出端子的电压不高于电压时，振荡器输出控制时钟信号对升压转换器的晶体管进行预定的时间和关断时间，以执行晶体管的切换控制; 并且当电压检测电路检测到输出端子的电压达到电压时，振荡器输出从选择电路输入到升压转换器的晶体管的接通时间和截止时间的控制时钟信号，以执行切换控制晶体管。

45. 发明授权

US08514013B2 Integrated circuit device having a plurality of integrated circuit chips and an interposer 有权
标题翻译：具有多个集成电路芯片和插入器的集成电路装置
公开(公告)号：US08514013B2
公开(公告)日：2013-08-20
申请号：US13093343
申请日：2011-04-25
申请人： Ken Takeuchi , Teruyoshi Hatanaka , Koichi Ishida , Tadashi Yasufuku , Makoto Takamiya , Takayasu Sakurai
发明人： Ken Takeuchi , Teruyoshi Hatanaka , Koichi Ishida , Tadashi Yasufuku , Makoto Takamiya , Takayasu Sakurai
IPC分类号： H01L25/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： The channel number detecting circuit detects the operation channel number based on the output terminal voltage after falling down when the output terminal voltage falls down during the voltage boosting control, and the switching control circuit generates the control clock signal having the on-time and the off-time adjusted based on the operation channel number and performs the voltage boosting control using generating control clock signal. The voltage boosting control is properly performed based on the operation channel number when the operation channel number increase during performing the voltage boosting control. Thus boosting the power supply voltage up to a second voltage is accomplished.
摘要翻译：通道号检测电路在升压控制期间当输出端子电压下降时，基于输出端子电压在下降之后检测操作通道数，并且开关控制电路产生具有导通时间和关断的控制时钟信号根据操作通道号进行时间调整，并使用产生控制时钟信号进行升压控制。当在执行升压控制期间操作通道号增加时，基于操作通道号适当地执行升压控制。从而实现将电源电压提高到第二电压。

46. 发明授权

US07768790B2 Electronic circuit 有权
标题翻译：电子电路
公开(公告)号：US07768790B2
公开(公告)日：2010-08-03
申请号：US10588769
申请日：2005-02-14
申请人： Tadahiro Kuroda , Daisuke Mizoguchi , Yusmeeraz Binti Yusof , Noriyuki Miura , Takayasu Sakurai
发明人： Tadahiro Kuroda , Daisuke Mizoguchi , Yusmeeraz Binti Yusof , Noriyuki Miura , Takayasu Sakurai
IPC分类号： H05K7/00
CPC分类号： H05K1/165 , H01F17/0006 , H01F2038/143 , H01L25/0657 , H01L2224/32145 , H01L2225/06527 , H05K1/0237 , H05K1/0239 , Y10T29/49002
摘要： An electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13a, 13b, 13c and the first through the third receiver coils 15a, 15b, 15c are formed by wiring on the first through the third LSI chips 11a, 11b, 11c. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications. The first through the third transmitter circuits 12a, 12b, 12c are connected to the first through the third transmitter coils 13a, 13b and 13c, respectively, and the first through the third receiver circuits 14a, 14b, 14c are connected to the first through the third receiver coils 15a, 15b, 15c, respectively.
摘要翻译：在三维或三维以上的基板上传输信号的情况下能够高效地发送信号的电子电路。在本发明中，将LSI芯片堆叠成三层，在三块芯片上形成总线。通过第一至第三LSI芯片11a，11b，11c上的布线形成第一至第三发送线圈13a，13b，13c和第一至第三接收线圈15a，15b，15c。这三对发射器和接收器线圈被布置成使得其开口的中心彼此重合，由此三对发射器和接收器线圈13和15形成感应耦合以实现通信。第一至第三发送器电路12a，12b，12c分别连接到第一至第三发送器线圈13a，13b和13c，并且第一至第三接收器电路14a，14b，14c连接到第一至第第三接收线圈15a，15b，15c。

47. 发明申请

US20070289772A1 Electronic Circuit 有权
标题翻译：电子电路
公开(公告)号：US20070289772A1
公开(公告)日：2007-12-20
申请号：US10588769
申请日：2005-02-14
申请人： Tadahiro Kuroda , Daisuke Mizoguchi , Yusmeeraz Yusof , Noriyuki Miura , Takayasu Sakurai
发明人： Tadahiro Kuroda , Daisuke Mizoguchi , Yusmeeraz Yusof , Noriyuki Miura , Takayasu Sakurai
IPC分类号： H01S4/00 , H05K1/16
CPC分类号： H05K1/165 , H01F17/0006 , H01F2038/143 , H01L25/0657 , H01L2224/32145 , H01L2225/06527 , H05K1/0237 , H05K1/0239 , Y10T29/49002
摘要： The present invention has an object to provide an electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13a, 13b, 13c and the first through the third receiver coils 15a, 15b, 15c are formed by wiring on the first through the third LSI chips 11a, 11b, 11c. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications. The first through the third transmitter circuits 12a, 12b, 12c are connected to the first through the third transmitter coils 13a, 13b and 13c, respectively, and the first through the third receiver circuits 14a, 14b, 14c are connected to the first through the third receiver coils 15a, 15b, 15c, respectively.
摘要翻译：本发明的目的是提供一种能够在三维或三维以上的基板上传输信号的情况下，有效地发送信号的电子电路。在本发明中，将LSI芯片堆叠成三层，在三块芯片上形成总线。通过在第一至第三LSI芯片11a，11b，11上的布线形成第一至第三发送线圈13a，13b，13c和第一至第三接收线圈15a，15b，15c， C。这三对发射器和接收器线圈被布置成使得其开口的中心彼此重合，由此三对发射器和接收器线圈13和15形成感应耦合以实现通信。第一至第三发送器电路12a，12b，12c分别连接到第一至第三发送器线圈13a，13b和13c，并且第一至第三接收器电路14a， 14c分别连接到第一至第三接收线圈15a，15b，15c。

48. 发明授权

US6037805A Integrated circuit device having small amplitude signal transmission 有权
标题翻译：具有小振幅信号传输的集成电路装置
公开(公告)号：US6037805A
公开(公告)日：2000-03-14
申请号：US280726
申请日：1999-03-29
申请人： Tadahiro Kuroda , Takayasu Sakurai
发明人： Tadahiro Kuroda , Takayasu Sakurai
IPC分类号： H03K19/0175 , G06F12/00 , G06F13/16 , H01L27/02 , H03K19/003 , H03K19/0185 , H03K19/096 , H04L25/02 , H01L25/00 , H03K19/00 , H03K19/094
CPC分类号： H01L27/0218 , H03K19/00384 , H03K19/018507 , H01L2224/05554 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/13091 , H01L2924/3011 , H01L2924/30111
摘要： To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.
摘要翻译：为了最小化功率消耗，所公开的半导体集成电路器件包括：用于产生固定在第一电源电压和第二电源电压之间的预定电压的偏置电路; 用于接收每个在第一和第二电源电压之间振动的反相输入信号和非反相输入信号的驱动器电路，用于将接收到的输入信号转换成在偏置电路的输出电压和第一电源电压之间振动的信号，并且用于通过转换的信号驱动传送路径; 用于分压偏置电路的输出电压的分压电路; 以及接收器电路，用于通过使用分压器电路的输出作为参考电压来检测用于驱动传输路径的信号，并且用于将检测到的信号转换为在第一电源电压和第二电源电压之间振动的信号。

49. 发明授权

US5673214A Discrete cosine transform processor 失效
标题翻译：离散余弦变换处理器
公开(公告)号：US5673214A
公开(公告)日：1997-09-30
申请号：US704922
申请日：1996-08-28
申请人： Lee-Sup Kim , Tetsu Nagamatsu , Takayasu Sakurai
发明人： Lee-Sup Kim , Tetsu Nagamatsu , Takayasu Sakurai
IPC分类号： H04N19/60 , G06F17/14 , G06T1/20 , G06T9/00 , H04N1/41 , H04N19/42 , H04N19/423 , H04N19/426 , H04N19/625
CPC分类号： G06F17/147 , G06T9/007
摘要： Disclosed is an improved discrete cosine transform processor comprising an input unit for receiving image data to be processed, a storage unit for previously storing a result of a multiplication and accumulation calculation effected beforehand with respect to image input data and transform matrix components so that the same value is read from the same read line; a decoding unit for selecting the read line, in which each bit value of the image input data composed of a plurality of bits serves as a piece of address data; an accumulation unit for accumulating the data read from the storage unit and an output unit for outputting a result of the accumulation processing as output data. The storage unit uses the common data in common when effecting the multiplication and accumulation calculation, and, hence, a storage capacity is reduced, thereby making it possible to decrease a chip area.
摘要翻译：公开了一种改进的离散余弦变换处理器，包括用于接收要处理的图像数据的输入单元，用于预先存储关于图像输入数据和变换矩阵分量预先实现的乘法和累加计算的结果的存储单元，使得相同值从相同的读取行读取; 用于选择读取行的解码单元，其中由多个位组成的图像输入数据的每个位值用作一段地址数据; 用于累积从存储单元读取的数据的积累单元和用于输出积累处理结果作为输出数据的输出单元。存储单元在进行乘法运算和累计运算时，共同使用共同的数据，因此能够减小存储容量，从而可以减少芯片面积。

50. 发明授权

US4618945A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4618945A
公开(公告)日：1986-10-21
申请号：US517419
申请日：1983-07-26
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096
摘要： A semiconductor memory device has a plurality of memory cells arranged in a two-dimensional matrix array, word lines for connecting memory cells of each row to a row decoder, and bit lines for connecting memory cells of each column to a column decoder. The word lines include first word lines each of which is connected to several memory cells in each column section of one row. The word lines also include a second word line connected to the first word lines of each row through corresponding switches. In response to a column address signal, one of the switches of each row is turned on, so that one of the first word lines is connected to the corresponding second word line.
摘要翻译：半导体存储器件具有布置在二维矩阵阵列中的多个存储器单元，用于将每行的存储单元连接到行解码器的字线和用于将每列的存储单元连接到列解码器的位线。字线包括第一字线，每条字线连接到一行的每个列部分中的多个存储器单元。字线还包括通过相应的开关连接到每行的第一字线的第二字线。响应于列地址信号，每行的开关之一被接通，使得第一字线中的一个连接到对应的第二字线。

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