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41. 发明授权

US07681154B2 Method for designing device, system for aiding to design device, and computer program product therefor 失效
标题翻译：设计装置的方法，辅助设计装置的系统及其计算机程序产品
公开(公告)号：US07681154B2
公开(公告)日：2010-03-16
申请号：US11854591
申请日：2007-09-13
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Hiroya Shimizu , Satoshi Isa , Satoshi Itaya , Yukitoshi Hirose
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.
摘要翻译：公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。第二半导体芯片包括耦合到输入焊盘的输出焊盘。调整对象被连接到第一和第二半导体芯片。主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

42. 发明授权

US07569428B2 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US07569428B2
公开(公告)日：2009-08-04
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L21/82 , H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

43. 发明申请

US20080012107A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080012107A1
公开(公告)日：2008-01-17
申请号：US11822265
申请日：2007-07-03
申请人： Satoshi Isa , Mitsuaki Katagiri , Kyoichi Nagata , Seiji Narui
发明人： Satoshi Isa , Mitsuaki Katagiri , Kyoichi Nagata , Seiji Narui
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01056 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.
摘要翻译：公开了一种半导体存储器件，其中芯片上的焊盘分别焊接到封装的焊球的焊盘上，所述焊盘分别布置在芯片的彼此面对的第一和第二侧上，并且设置在第三侧的芯片以及。四组用于数据信号的焊盘分别设置在通过将第一和第二侧划分成四个区域而获得的四个区域上。用于命令/地址信号的板被布置在第三侧上，从而增加了用于数据信号的接合点的布局空间，并实现了数据信号的布线的均匀性。

44. 发明申请

US20070069362A1 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US20070069362A1
公开(公告)日：2007-03-29
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

45. 发明申请

US20070057380A1 Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package 失效
标题翻译：半导体装置的设计方法，辅助设计半导体装置的系统，其计算机程序产品和半导体封装
公开(公告)号：US20070057380A1
公开(公告)日：2007-03-15
申请号：US11511438
申请日：2006-08-29
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
IPC分类号： H01L23/48
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
摘要翻译：公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。决定设计指南来解决确定的问题部分。

46. 发明授权

US07714424B2 Stacked-type semiconductor package 有权
标题翻译：堆叠型半导体封装
公开(公告)号：US07714424B2
公开(公告)日：2010-05-11
申请号：US12081264
申请日：2008-04-14
申请人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
发明人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/105 , H01L2224/50 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
摘要翻译：与第一半导体芯片的第一信号传输路径中的第一路径部分的对应部分是互连部件和第二路径部分，到第二半导体芯片的第二信号传输路径，并且不形成在第一条带上。允许第二信号传输路径的电长度独立于第一带被调整，使得第二信号传输路径的电长度可以容易地等于或基本等于第一信号传输路径的电长度。

47. 发明授权

US07546506B2 DRAM stacked package, DIMM, and semiconductor manufacturing method 失效
标题翻译： DRAM堆叠封装，DIMM和半导体制造方法
公开(公告)号：US07546506B2
公开(公告)日：2009-06-09
申请号：US11378368
申请日：2006-03-20
申请人： Yuji Sonoda , Shuji Kikuchi , Katsunori Hirano , Ichiro Anjo , Mitsuaki Katagiri
发明人： Yuji Sonoda , Shuji Kikuchi , Katsunori Hirano , Ichiro Anjo , Mitsuaki Katagiri
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C5/04 , G11C2029/2602 , G11C2029/5602
摘要： The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.
摘要翻译：本发明涉及一种DRAM堆叠封装，一种DIMM，一种用于测试它们的方法以及一种半导体制造方法。根据本发明，提供了一种DRAM堆叠封装，包括：多个堆叠的DRAM; 连接测试设备的外部终端，所述外部终端至少用于输入/输出地址，命令和数据; 以及设置在所述多个堆叠的DRAM和所述外部端子之间的接口芯片。多个DRAM和接口芯片被实现在封装上。接口芯片包括：测试电路，包括：算法模式发生器，用于产生用于测试多个DRAM的测试模式; 施加用于将所述生成的测试图案应用于所述多个DRAM的电路; 以及用于将从多个DRAM接收的每个响应信号与用于判断的期望值进行比较的比较器。

48. 发明授权

US07466577B2 Semiconductor storage device having a plurality of stacked memory chips 有权
标题翻译：具有多个层叠的存储芯片的半导体存储装置
公开(公告)号：US07466577B2
公开(公告)日：2008-12-16
申请号：US11392805
申请日：2006-03-30
申请人： Tomonori Sekiguchi , Hideki Osaka , Tatemi Ido , Osamu Nagashima , Mitsuaki Katagiri , Ichiro Anjo
发明人： Tomonori Sekiguchi , Hideki Osaka , Tatemi Ido , Osamu Nagashima , Mitsuaki Katagiri , Ichiro Anjo
IPC分类号： G11C5/02 , G11C5/06 , H01L23/02 , H01L23/48
CPC分类号： G11C8/12 , G11C5/02 , G11C5/04 , G11C11/4074 , G11C11/4096 , H01L24/50
摘要： A semiconductor storage employs a base substrate (101) having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips (110) to (113) mounted on a base substrate (101), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (120). The interface chip (120) has a chip select signal generation circuit that can individually activate a plurality of memory chips (110) to (113) on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).
摘要翻译：半导体存储器使用具有命令/地址外部端子组（CA），数据输入/输出外部端子组（DQ）和单个芯片选择外部端子（CS）的基底（101），并且还包括多个的安装在基板（101）上的存储芯片（110）至（113），每个可独立地进行读写操作。端子（CA），（DQ）和（CS）连接到接口芯片（120）。接口芯片（120）具有芯片选择信号生成电路，该电路可以基于通过终端（CA）馈送的地址信号，并基于以下方式单独激活多个存储器芯片（110）〜（113）通过端子（CS）馈送的芯片选择信号。

49. 发明申请

US20050230829A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050230829A1
公开(公告)日：2005-10-20
申请号：US11081658
申请日：2005-03-17
申请人： Yuji Watanabe , Mitsuaki Katagiri , Hisashi Tanie , Atsushi Nakamura , Tomohiko Sato
发明人： Yuji Watanabe , Mitsuaki Katagiri , Hisashi Tanie , Atsushi Nakamura , Tomohiko Sato
IPC分类号： H05K1/02 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/31 , H01L23/48 , H01L25/065 , H01L25/10 , H01L25/18 , H05K1/11 , H05K3/34
CPC分类号： H05K1/111 , H01L21/563 , H01L23/3114 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/73203 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06565 , H01L2924/00014 , H01L2924/01087 , H01L2924/15311 , H01L2924/181 , H05K2201/09281 , H05K2201/094 , H05K2201/10734 , Y02P70/611 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is provided with a semiconductor package 2 and a package substrate 5 having lands 8 that electrically connect by way of solder bumps 4 to the semiconductor package 2. A plurality of columns, in each of which a multiplicity of lands 8 are arranged, are formed on the package substrate 5. At least one of the lands 8 that make up columns that are located closest to each of the main sides that make up the outer edges of the semiconductor package has an interconnection 9 that extends from the land 8 along the surface of the package substrate. The interconnection 9 is formed such that the part that contacts the land 8 is located closer to a line that passes through the center of the land 8 and that is orthogonal to a line that connects the center of the land 8 with the center of the semiconductor package 2 than to the line that connects the center of the land 8 with the center of the semiconductor package 2.
摘要翻译：半导体器件设置有半导体封装2和封装衬底5，封装衬底5具有通过焊料凸点4电连接到半导体封装2的焊盘8。在封装基板5上形成有多个列，其中布置有多个焊盘8。构成最靠近构成半导体封装的外边缘的每个主侧的列的焊盘8中的至少一个具有从焊盘8沿着封装基板的表面延伸的互连9。互连9形成为使得接触焊盘8的部分更靠近通过焊盘8的中心的线并且与连接焊盘8的中心与半导体的中心的线垂直的线封装2，而不是将焊盘8的中心与半导体封装2的中心连接的线。

50. 发明申请

US20050230824A1 BGA semiconductor device having a dummy bump 有权
标题翻译： BGA半导体器件具有虚拟凸块
公开(公告)号：US20050230824A1
公开(公告)日：2005-10-20
申请号：US11105546
申请日：2005-04-14
申请人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
发明人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
IPC分类号： H01L23/12 , H01L21/60 , H01L23/31 , H01L23/48 , H01L23/498 , H05K3/30 , H05K3/34
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.
摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

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