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41. 发明申请

US20120044777A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120044777A1
公开(公告)日：2012-02-23
申请号：US13215217
申请日：2011-08-22
申请人： Hidehiro FUJIWARA , Koji NII , Makoto Yabuuchi , Kazutami Arimoto
发明人： Hidehiro FUJIWARA , Koji NII , Makoto Yabuuchi , Kazutami Arimoto
IPC分类号： G11C7/00
CPC分类号： G11C16/20 , G11C7/24 , G11C29/44
摘要： By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.
摘要翻译：通过使用片上嵌入式存储器中的位错误发生在随机地址处的事实，提供了用于创建芯片唯一ID并利用该ID的装置。已经从外部接收到验证请求的控制器指示可变电源电路将提供给存储器的电压降低到低于正常操作时间的电压。当提供给存储器的电压稳定时，控制器向存储器BIST请求存储器测试。通过使用由于存储器测试的结果而出现错误的地址，控制器创建芯片唯一ID，并使用ID作为对验证请求的响应。

42. 发明授权

US08098080B2 Semiconductor programmable device 有权
标题翻译：半导体可编程器件
公开(公告)号：US08098080B2
公开(公告)日：2012-01-17
申请号：US12919356
申请日：2008-12-24
申请人： Kazutami Arimoto
发明人： Kazutami Arimoto
IPC分类号： G06F7/38 , H01L25/00
CPC分类号： H03K19/17756 , H03K19/1733
摘要： An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.
摘要翻译： ePLX单元包括具有SRAM和MUX的逻辑单元，以及具有用于在逻辑单元中建立布线连接的SRAM和TG的开关单元。当复合模块被设置为第一模式时，加法/标志控制单元分别使用SRAM作为数据字段和标志字段，以依照下述方式自主地控制每个数据字段和标志字段的读取地址存储在标志字段中的控制标志。此外，当复合模块被设置为第二模式时，加法/标志控制单元将配置信息写入每个SRAM以重新配置逻辑电路。因此，电路配置的粒度可以变化，这允许在配置功能时提高灵活性。

43. 发明授权

US07910975B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07910975B2
公开(公告)日：2011-03-22
申请号：US10593275
申请日：2005-06-03
申请人： Fukashi Morishita , Kazutami Arimoto
发明人： Fukashi Morishita , Kazutami Arimoto
IPC分类号： H01L29/788 , H01L27/01 , H01L27/12
CPC分类号： G11C11/405 , G11C2211/4016 , H01L27/108 , H01L27/10802
摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.
摘要翻译：本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。栅电极连接到栅极线，杂质扩散区连接到源极线。存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。杂质扩散区域连接到位线。

44. 发明申请

US20100179976A1 SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING 审中-公开
标题翻译：执行操作处理的半导体器件
公开(公告)号：US20100179976A1
公开(公告)日：2010-07-15
申请号：US12687756
申请日：2010-01-14
申请人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
发明人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
IPC分类号： G06F7/44 , G06F5/01 , G06F7/552
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
摘要翻译：半导体器件包括：解码器，接收根据布斯（Booth）算法的3比特的第一乘法器数据，指示乘法器输出移位标志，反转标志和操作标志，第一部分乘积计算单元接收2位的第一被乘数数据指示被乘数，移位标志，反转标志和操作标志，以基于移位标志来选择第一被乘数数据的高位位和低位位之一，基于该选择位反转或非反转所选位反转标志，基于操作标志选择反相或非反相数据和预定逻辑电平的数据之一，并将选择的数据作为指示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。

45. 发明授权

US07480168B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07480168B2
公开(公告)日：2009-01-20
申请号：US11819583
申请日：2007-06-28
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑并入的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

46. 发明授权

US07139208B2 Refresh-free dynamic semiconductor memory device 失效
公开(公告)号：US07139208B2
公开(公告)日：2006-11-21
申请号：US11165273
申请日：2005-06-24
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C7/20 , G11C5/14
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

47. 发明授权

US06909658B2 Semiconductor memory device with row selection control circuit 失效
标题翻译：具有行选择控制电路的半导体存储器件
公开(公告)号：US06909658B2
公开(公告)日：2005-06-21
申请号：US10842465
申请日：2004-05-11
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C2207/104
摘要： A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.
摘要翻译：将自刷新定时器持续设置为使周期性地刷新请求信号FAY活动的操作状态。当在刷新请求信号FAY和外部施加的读取/写入命令之间发生争用时，行选择相关电路/命令生成相关电路控制与行相关的控制信号，使得在例如读取或写入命令之后执行刷新操作写操作结束。子存储阵列SMA被划分为比常规情况更小的刷新周期，并且刷新周期在更短的时间段内结束。因此，可以在读周期时间内完成读操作和刷新操作。可以实现可以使用与SRAM的控制一样简单的DRAM内核。

48. 发明授权

US06781915B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06781915B2
公开(公告)日：2004-08-24
申请号：US10274872
申请日：2002-10-22
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C800
CPC分类号： G11C7/18 , G11C11/405 , G11C11/4097 , G11C2211/4013 , H01L27/108 , H01L27/10897
摘要： Memory cells are arranged such that one-bit data is stored by two-bit memory cells. The cell plate electrode of the memory cell capacitor and the gate electrode of the memory cell transistor are formed in the same manufacturing step. The amplitude of an isolation control signal applied to a bit line isolation gate connecting the bit line and the sense amplifier is restricted, and the word line is driven according to a negative voltage non-boosted word line scheme. A well region where a memory block is formed and a well region where the isolation gate is formed are separately provided, and separate bias voltages are applied thereto. Thus, a DRAM (dynamic random access memory)-based logic merged memory is implemented without degrading dielectric breakdown characteristics of the gate insulating film.
摘要翻译：存储单元被布置成使得一位数据由两位存储器单元存储。存储单元电容器的单元板电极和存储单元晶体管的栅极形成在相同的制造步骤中。施加到连接位线和读出放大器的位线隔离栅的隔离控制信号的幅度受到限制，并且字线根据负电压非升压字线方案被驱动。形成存储块的阱区和形成隔离栅的阱区分开设置，并且分别施加偏置电压。因此，实现基于DRAM（动态随机存取存储器）的逻辑合并存储器而不降低栅极绝缘膜的绝缘击穿特性。

49. 发明授权

US06608795B2 Semiconductor device including memory with reduced current consumption 失效
公开(公告)号：US06608795B2
公开(公告)日：2003-08-19
申请号：US10277879
申请日：2002-10-23
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4082 , G11C11/4087 , G11C2207/104
摘要： When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.

50. 发明授权

US06507532B1 Semiconductor memory device having row-related circuit operating at high speed 失效
标题翻译：具有行相关电路的半导体存储器件以高速工作
公开(公告)号：US06507532B1
公开(公告)日：2003-01-14
申请号：US09722687
申请日：2000-11-28
申请人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
发明人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/18 , G11C11/4087
摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.
摘要翻译：中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号时钟周期，用于传输到每个存储器子块。备用确定电路与时钟信号异步地执行备用确定。可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

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