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41. 发明申请

US20190220856A1 TECHNIQUES FOR CONDUCTING TRANSACTIONS UTILIZING CRYPTOCURRENCY 审中-公开
公开(公告)号：US20190220856A1
公开(公告)日：2019-07-18
申请号：US15870574
申请日：2018-01-12
申请人： Xi Li , Wen Zhao Cheng , Jun Ryan Menorca Tagama , Satrajit Ray , Gabriel Jin Juan Ang , Lavanya Rengarajan
发明人： Xi Li , Wen Zhao Cheng , Jun Ryan Menorca Tagama , Satrajit Ray , Gabriel Jin Juan Ang , Lavanya Rengarajan
IPC分类号： G06Q20/38 , G06Q20/40 , G06Q20/06
CPC分类号： G06Q20/3823 , G06Q20/065 , G06Q20/401 , H04L2209/56
摘要： Embodiments of the invention are directed to systems and methods for conducting a transaction utilizing a cryptocurrency. The user may fund a cryptocurrency account with his pre-existing cryptocurrency. An issuer may purchase cryptocurrency within a cryptocurrency exchange. The user may then utilize a payment device (e.g., a Crypto Debit Card) that is associated with a cryptocurrency balance to conduct a transaction with a merchant for goods and/or services. An authorization request message may be transmitted to the authorizing entity computer. The authorizing entity computer may determine a cryptocurrency amount corresponding to the fiat currency transaction amount of the authorization request message. A sell request message may be transmitted to an exchange that facilitates the sale of the cryptocurrency amount. If the sale is successful, the authorizing entity computer may transmit an authorization response message indicating that the transaction is approved and the merchant may release the purchased goods and/or services.

42. 发明授权

US08947924B2 Data readout circuit of phase change memory 有权
标题翻译：相变存储器的数据读出电路
公开(公告)号：US08947924B2
公开(公告)日：2015-02-03
申请号：US13202963
申请日：2011-06-24
申请人： Xi Li , Houpeng Chen , Zhitang Song , Daolin Cai
发明人： Xi Li , Houpeng Chen , Zhitang Song , Daolin Cai
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0026 , G11C2013/0054
摘要： A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result. Compared with the prior art, the data readout circuit of phase change memory provided by the present invention can effectively enhance the data readout speed, decrease the misreading window between high resistance state and low resistance state, reduce the crosstalk of data readout, and improve the reliability of data readout.
摘要翻译：一种相变存储器的数据读出电路，涉及一个或多个相变存储单元，其中每个相变存储单元通过位线和字线连接到控制电路; 所述数据读出电路包括：钳位电压发生电路，用于产生钳位电压; 预充电电路，用于在钳位电压的控制下快速充电位线; 夹紧电流产生电路，用于产生钳位电流，以在钳位电压的控制下将位线保持在钳位状态; 钳位电流运行电路，用于对钳位电流进行减法和乘法，以增加高电阻状态和低电阻状态之间的钳位电流差; 一个读出放大器电路，用于比较工作钳位电流和参考电流，并输出读出结果。与现有技术相比，本发明提供的相变存储器的数据读出电路可以有效提高数据读出速度，减少高电阻状态和低电阻状态之间的误读窗口，减少数据读出的串扰，数据读出的可靠性。

43. 发明授权

US08455327B2 Trench capacitor with spacer-less fabrication process 失效
公开(公告)号：US08455327B2
公开(公告)日：2013-06-04
申请号：US13198100
申请日：2011-08-04
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/0692 , H01L21/3081 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.

44. 发明申请

US20120104500A1 SHALLOW TRENCH ISOLATION RECESS REPAIR USING SPACER FORMATION PROCESS 失效
标题翻译：使用间隙形成过程进行浅层分离分离修复
公开(公告)号：US20120104500A1
公开(公告)日：2012-05-03
申请号：US12914095
申请日：2010-10-28
申请人： Ming Cai , Xi Li , Frank D. Tamweber, JR.
发明人： Ming Cai , Xi Li , Frank D. Tamweber, JR.
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823468
摘要： A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon.
摘要翻译：形成半导体器件的方法包括在多个晶体管栅极结构上形成间隔层，晶体管栅极结构形成在衬底的有源和浅沟槽隔离（STI）区域上。对间隔层进行定向蚀刻以形成与多个晶体管栅极结构相邻的侧壁间隔物，并且间隔层的水平填充部分保留在STI区域中存在的多个凹部中，以使STI区域基本平坦化在其之后的材料沉积之前。

45. 发明申请

US20080173977A1 POST STI TRENCH CAPACITOR 失效
标题翻译： POST STI TRENCH电容器
公开(公告)号：US20080173977A1
公开(公告)日：2008-07-24
申请号：US11624385
申请日：2007-01-18
申请人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L29/94 , H01L27/0805 , H01L28/91 , H01L29/66181
摘要： A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成具有用于去耦应用的适当大值的电容器。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

46. 外观设计

USD977585S1 Toy panel 有权
公开(公告)号：USD977585S1
公开(公告)日：2023-02-07
申请号：US29732970
申请日：2020-04-29
申请人： Xi Li
设计人： Xi Li

47. 发明授权

US08901005B2 Method for simultaneously forming features of different depths in a semiconductor substrate 有权
标题翻译：同时形成半导体衬底中不同深度的特征的方法
公开(公告)号：US08901005B2
公开(公告)日：2014-12-02
申请号：US13865223
申请日：2013-04-18
申请人： Habib Hichri , Xi Li , Richard Wise
发明人： Habib Hichri , Xi Li , Richard Wise
IPC分类号： H01L21/311 , H01L21/84 , H01L21/3065 , H01L21/762 , H01L27/108 , H01L29/66
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
摘要翻译：本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层层和氮化物层上的氧化硅层。然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。然后用第一蚀刻气体蚀刻第一开口和第二开口。然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

48. 发明授权

US08209069B1 Aircraft sensor anticipator system 有权
标题翻译：飞机传感器预报系统
公开(公告)号：US08209069B1
公开(公告)日：2012-06-26
申请号：US12429362
申请日：2009-04-24
申请人： Frank A. McLoughlin , Xi Li
发明人： Frank A. McLoughlin , Xi Li
IPC分类号： G05D1/00
CPC分类号： G01C21/165
摘要： An apparatus and method for estimating future pitch and roll angles of an aircraft to compensate for a time delay caused by a flight instrumentation system calculating the aircraft's pitch and roll. The apparatus may output signals to an aircraft autopilot system. The apparatus may comprise various inputs and outputs, at least one compensation module, and at least one addition module. The compensation module may multiply a gain value by the pitch rate of the aircraft and by the roll rate of the aircraft to determine a pitch compensation amount and a roll compensation amount. Then the pitch compensation amount may be added to the pitch of the aircraft, and the roll compensation amount may be added to the roll of the aircraft to solve for a compensated pitch and a compensated roll to send to the autopilot system.
摘要翻译：一种用于估计飞机未来俯仰角和倾斜角度的装置和方法，以补偿由飞行仪表系统计算飞机的俯仰和滚动所引起的时间延迟。该装置可以向飞行器自动驾驶仪系统输出信号。该装置可以包括各种输入和输出，至少一个补偿模块和至少一个附加模块。补偿模块可以将增益值乘以飞行器的俯仰速率和飞行器的滚转速率，以确定俯仰补偿量和滚转补偿量。然后，可以将俯仰补偿量加到飞行器的俯仰上，并且可以将滚动补偿量加到飞行器的卷上，以解决补偿桨距和补偿滚轮以发送给自动驾驶仪系统。

49. 发明公开

US20230198124A1 RADIO FREQUENCY SWITCH 审中-公开
公开(公告)号：US20230198124A1
公开(公告)日：2023-06-22
申请号：US17552619
申请日：2021-12-16
申请人： Chuanzhao Yu , Hyun Yoon , Muhammed Elgousi , Xi Li , LiChung Tony Chang
发明人： Chuanzhao Yu , Hyun Yoon , Muhammed Elgousi , Xi Li , LiChung Tony Chang
IPC分类号： H01Q1/22 , H03K17/687 , H03H11/04
CPC分类号： H01Q1/2283 , H03K17/687 , H03H11/04
摘要： A wireless communication device can include switch circuitry. The switch circuitry can include stacks having a common gate node and a common body node, wherein a stack includes a metal-oxide-semiconductor field-effect transistor (MOSFET) having a body resistive element coupled to a body terminal of the MOSFET and the common body node a gate resistive element coupled to a gate terminal of the MOSFET and the common gate node. The switch circuitry can further include a self-biased MOSFET coupled to the common gate node and the common body node, a gate of the self-biased MOSFET configured to receive direct current (DC) bias with a low pass filter.

50. 外观设计

USD973138S1 Toy piano 有权
公开(公告)号：USD973138S1
公开(公告)日：2022-12-20
申请号：US29759949
申请日：2020-11-26
申请人： Xi Li
设计人： Xi Li

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