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41. 发明申请

US20110156801A1 TAMPER RESISTANT FUSE DESIGN 有权
标题翻译：防潮保险丝设计
公开(公告)号：US20110156801A1
公开(公告)日：2011-06-30
申请号：US12651341
申请日：2009-12-31
申请人： Xianghong Tong , Zhanping Chen , Kevin X. Zhang , Zhiyong Ma , Kevin D. Johnson , Jun He
发明人： Xianghong Tong , Zhanping Chen , Kevin X. Zhang , Zhiyong Ma , Kevin D. Johnson , Jun He
IPC分类号： H01H85/00
CPC分类号： H01L23/5256 , G11C8/20 , G11C17/16 , H01L23/576 , H01L2924/0002 , H01L2924/00
摘要： A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
摘要翻译：通常提供防篡改保险丝设计。在这方面，引入一种在集成电路装置中包括多个熔丝的装置，用于存储与熔丝并联的值和多个电阻，其中每个熔丝包括并联电阻器，以提供围绕熔丝的潜在耗散路径。还描述和要求保护其他实施例。

42. 发明授权

US07402519B2 Interconnects having sealing structures to enable selective metal capping layers 有权
标题翻译：具有密封结构以实现选择性金属覆盖层的互连
公开(公告)号：US07402519B2
公开(公告)日：2008-07-22
申请号：US11144576
申请日：2005-06-03
申请人： Jun He , Kevin J. Fischer , Ying Zhou , Peter K. Moon
发明人： Jun He , Kevin J. Fischer , Ying Zhou , Peter K. Moon
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/0217 , H01L21/02252 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76844 , H01L21/76856 , H01L21/76865 , H01L21/76877 , H01L21/76888 , H01L23/5283 , H01L23/53209 , H01L23/53228 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
摘要翻译：制造用于微电子器件的封盖互连的方法，其包括封盖层和互连件之间的任何间隙的密封特征以及由其形成的结构。密封特征改善了互连的封装，其基本上减少或防止导电材料从封盖互连件的电迁移和/或扩散。

43. 发明授权

US07402509B2 Method of forming self-passivating interconnects and resulting devices 有权
标题翻译：形成自钝化互连和所产生的器件的方法
公开(公告)号：US07402509B2
公开(公告)日：2008-07-22
申请号：US11081187
申请日：2005-03-16
申请人： Mauro J. Kobrinsky , Jun He , Kevin O'Brien , Patrick Morrow , Ying Zhou , Shriram Ramanathan
发明人： Mauro J. Kobrinsky , Jun He , Kevin O'Brien , Patrick Morrow , Ying Zhou , Shriram Ramanathan
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L21/76867 , B23K35/302 , H01L21/76852 , H01L21/76885 , H01L21/76886 , H01L21/76888 , H01L24/11 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05547 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13099 , H01L2224/13147 , H01L2224/81801 , H01L2224/81894 , H01L2224/9202 , H01L2225/06513 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19043 , H01L2224/48 , H01L2924/013
摘要： A method of forming self-passivating interconnects. At least one of two mating bond structures is formed, at least in part, from an alloy of a first metal and a second metal (or other element). The second metal is capable of migrating through the first metal to free surfaces of the mating bond structures. During bonding, the two mating bond structures are bonded together to form an interconnect, and the second metal segregates to free surfaces of this interconnect to form a passivation layer. Other embodiments are described and claimed.
摘要翻译：一种形成自钝化互连的方法。至少部分地由第一金属和第二金属（或其它元素）的合金形成两个匹配结合结构中的至少一个。第二金属能够通过第一金属迁移到配合结合结构的自由表面。在接合期间，两个配对结合结构结合在一起以形成互连，并且第二金属分离到该互连的自由表面以形成钝化层。描述和要求保护其他实施例。

44. 发明申请

US20080122078A1 Systems and methods to passivate on-die redistribution interconnects 审中-公开
标题翻译：钝化片上再分配互连的系统和方法
公开(公告)号：US20080122078A1
公开(公告)日：2008-05-29
申请号：US11595645
申请日：2006-11-08
申请人： Jun He , Kevin J. Lee , Kaustabh Gadre , Subhash Joshi
发明人： Jun He , Kevin J. Lee , Kaustabh Gadre , Subhash Joshi
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L23/525 , H01L21/76834 , H01L21/76886 , H01L21/76888 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02333 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/11912 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/05552
摘要： An integrated circuit apparatus comprises a semiconductor substrate having a plurality of devices formed thereon, one or more metallization layers to interconnect the plurality of devices, and a bond pad formed over the one or more metallization layers and electrically coupled to at least one of the metallization layers. A first passivation layer is formed over the bond pad and over the metallization layers and a redistribution interconnect formed on the passivation layer. A first via formed through the first passivation layer electrically couples the redistribution interconnect to the bond pad. A second passivation layer is formed on the redistribution interconnect to prevent thermomechanical degradation and improve electromigration performance. A dielectric layer is formed on the second passivation layer and a die-side bump is formed on the dielectric layer. A second via formed through the dielectric layer and through the second passivation layer electrically couples the die-side bump to the redistribution interconnect.
摘要翻译：集成电路装置包括具有形成在其上的多个器件的半导体衬底，用于互连多个器件的一个或多个金属化层以及形成在所述一个或多个金属化层上的接合焊盘，并且电连接至至少一个金属化层层。第一钝化层形成在接合焊盘上方和金属化层上方，以及形成在钝化层上的再分布互连。通过第一钝化层形成的第一通孔将再分布互连电耦合到接合焊盘。在再分布互连上形成第二钝化层以防止热机械降解并改善电迁移性能。在第二钝化层上形成电介质层，在电介质层上形成裸片侧凸点。通过电介质层形成的第二通孔和通过第二钝化层电连接裸片侧凸起与再分布互连。

45. 发明授权

US07332741B2 Multidirectional leakage path test structure 失效
标题翻译：多向泄漏路径测试结构
公开(公告)号：US07332741B2
公开(公告)日：2008-02-19
申请号：US10996365
申请日：2004-11-26
申请人： Mon-Chin Tsai , Xinghua Pu , Ning Jiang , Jun He
发明人： Mon-Chin Tsai , Xinghua Pu , Ning Jiang , Jun He
IPC分类号： H01L29/40
CPC分类号： G01R31/025 , H01L22/34
摘要： A test structure for testing a multidirectional current leakage path. A first doped region of a first conductivity is in the first well of the first conductivity in a substrate, in which the first doped region has a dopant concentration higher than the first well has. A first contact is on the first doped region and contacts the first doped region. The first contact has first and second portions respectively parallel to the first and second directions. A plurality of second doped regions of a second conductivity are in the first well and isolated from the first doped region. In a third direction, the second regions are adjacent to each another and isolate the first portion from the second portion. A plurality of second contacts are on the second doped regions and each one is corresponding to each the second doped region. With a relative shift between the first contact and the second doped region, the partial overlap is used in the test of a multidirectional leakage path.
摘要翻译：用于测试多向电流泄漏路径的测试结构。第一导电性的第一掺杂区域在衬底中位于第一导电性的第一阱中，其中第一掺杂区域具有高于第一阱的掺杂剂浓度。第一接触在第一掺杂区域上并接触第一掺杂区域。第一触点具有分别平行于第一和第二方向的第一和第二部分。具有第二导电性的多个第二掺杂区域位于第一阱中并与第一掺杂区隔离。在第三方向上，第二区域彼此相邻并且将第一部分与第二部分隔离。多个第二触点位于第二掺杂区域上，并且每个第二触点对应于每个第二掺杂区域。通过第一接触和第二掺杂区域之间的相对移动，在多向泄漏路径的测试中使用部分重叠。

46. 发明申请

US20070164272A1 Three-terminal electrical bistable devices 有权
标题翻译：三端电气双稳态器件
公开(公告)号：US20070164272A1
公开(公告)日：2007-07-19
申请号：US10581797
申请日：2004-12-01
申请人： Yang Yang , Liping Ma , Jun He
发明人： Yang Yang , Liping Ma , Jun He
IPC分类号： H01L29/08
CPC分类号： H01L51/0504 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2213/15 , G11C2213/55 , H01L51/0036 , H01L51/0039 , H01L51/004 , H01L51/0043 , H01L51/0067 , H01L51/05
摘要： A three terminal electrical bistable device that includes a tri-layer composed of an electrically conductive mixed layer sandwiched between two layers of low conductivity organic material that is interposed between a top electrode and a bottom electrode. The conducting mixed layer serves as the middle electrode. The device includes two memory cells composed of electrode/organic layer/mixed layer, where the interfaces between the electrically conductive mixed layer and the low conductivity organic layer exhibit bistable behavior.
摘要翻译：一种三端电双稳态器件，其包括夹在介于顶电极和底电极之间的两层低电导有机材料之间的导电混合层组成的三层。导电混合层用作中间电极。该装置包括由电极/有机层/混合层组成的两个存储单元，其中导电混合层和低电导率有机层之间的界面呈现双稳态。

47. 发明申请

US20070056381A1 Method Of Determining Stress 失效
标题翻译：确定应力的方法
公开(公告)号：US20070056381A1
公开(公告)日：2007-03-15
申请号：US11554574
申请日：2006-10-30
申请人： Jun He , Jun Zhao , Ming Tan
发明人： Jun He , Jun Zhao , Ming Tan
IPC分类号： G06F15/16
CPC分类号： G01L1/2293 , G01L1/18
摘要： A micromachined strain gauge comprising a plastically deformable piezoresistive microstructure formed on a surface of a substrate so that deformation of the substrate plastically deforms the microstructure to thereby change the resistance of the microstructure. The stress in the substrate can be determined from the change in the resistance of the microstructure.
摘要翻译：微机械应变仪包括形成在基板表面上的可塑变形的压阻微结构，使得基板的变形使微结构变形，从而改变微观结构的电阻。基板中的应力可以根据微结构的电阻变化来确定。

48. 发明授权

US07077998B2 Catalytic cracking reaction-regeneration system 失效
公开(公告)号：US07077998B2
公开(公告)日：2006-07-18
申请号：US10304748
申请日：2002-11-27
申请人： Xuefeng Wu , Jun He , Zhanfeng Zhang , Xianglin Yu , Xiaoxiang Zhong
发明人： Xuefeng Wu , Jun He , Zhanfeng Zhang , Xianglin Yu , Xiaoxiang Zhong
IPC分类号： B01J8/12 , B01J8/26 , B01J8/36
CPC分类号： B01J8/0055 , B01J8/228 , B01J8/26 , C10G11/18 , C10G11/182
摘要： A catalytic cracking reaction-regeneration system, comprising a regenerator, a settler, a gas-solid separator, a buffer, a riser reactor, a horizontal reaction tube, a catalyst delivery pipe, and a down-flow reactor. This system can be used for experiments and researches on various processes such as riser catalytic cracking, sectional feeding, instantaneous contact, and down-flow catalytic cracking and can be used for catalyst evaluation tests. This abstract is neither intended to define the invention disclosed in this specification nor intended to limit the scope of the invention in any way.

49. 发明授权

US06998216B2 Mechanically robust interconnect for low-k dielectric material using post treatment 失效
标题翻译：使用后处理的低k电介质材料的机械稳健互连
公开(公告)号：US06998216B2
公开(公告)日：2006-02-14
申请号：US10253723
申请日：2002-09-24
申请人： Jun He , Jihperng Leu
发明人： Jun He , Jihperng Leu
IPC分类号： G03C5/00 , H01L21/31
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76808 , H01L21/7682 , H01L21/76825 , H01L23/5222 , H01L23/5226 , H01L2924/0002 , Y10S430/143 , H01L2924/00
摘要： In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.
摘要翻译：在一个实施例中，在电介质层中的光致抗蚀剂（PR）沟槽图案的通孔上方形成沟槽。沟槽由两个侧壁部分和基部限定。通过使用PR沟槽图案作为掩模的后处理对侧壁的基部进行局部处理，以增强在基部下方的介电层的部分的机械强度。种子和阻挡层沉积在沟槽和通孔上。沟槽和通孔填充有金属层。在另一个实施例中，沟槽由电介质层中的PR沟槽图案形成。沉积并蚀刻柱PR以限定具有柱表面的柱开口。通过后处理在柱面上局部处理立柱开口，以提高柱表面下方的电介质层的部分的机械强度。

50. 外观设计

USD985668S1 Erasable doodle book 有权
公开(公告)号：USD985668S1
公开(公告)日：2023-05-09
申请号：US29836402
申请日：2022-04-26
申请人： Jun He
设计人： Jun He
摘要： FIG. 1 is a perspective view of an erasable doodle book, showing my new design;
FIG. 2 is an alternative perspective view of the erasable doodle book in an open state;
FIG. 3 is a front elevation view of FIG. 1;
FIG. 4 is a rear elevation view thereof;
FIG. 5 is a left-side elevation view thereof;
FIG. 6 is a right-side elevation view thereof;
FIG. 7 is a top plan view thereof; and,
FIG. 8 is a bottom plan view thereof.
The broken lines depict inner portions of the erasable doodle book in an open state, and form no part of the claimed design.

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