专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07323349B2 Self-aligned cross point resistor memory array 有权
标题翻译：自对准交叉点电阻存储器阵列
公开(公告)号：US07323349B2
公开(公告)日：2008-01-29
申请号：US11120385
申请日：2005-05-02
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Wei-Wei Zhuang
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.
摘要翻译：制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

42. 发明授权

US07297564B1 Fabrication of vertical sidewalls on (110) silicon substrates for use in Si/SiGe photodetectors 有权
标题翻译：在Si / SiGe光电探测器中用于（110）硅衬底上的垂直侧壁的制造
公开(公告)号：US07297564B1
公开(公告)日：2007-11-20
申请号：US11416985
申请日：2006-05-02
申请人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/1812 , Y02E10/50
摘要： A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors includes preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface. Masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane and etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer having vertical silicon (111) sidewalls. Removing the mask; growing SiGe-containing layers on the patterned silicon (110) layer; and fabricating a photodetector.
摘要翻译：在Si / SiGe光电探测器中使用的在硅（110）衬底上制造垂直侧壁的方法包括制备硅（110）层，其中硅（110）平面平行于下面的硅晶片表面。屏蔽具有平行于硅（111）层平面的掩模侧壁的硅（110）层并蚀刻硅（110）层以去除其未掩蔽部分，留下具有垂直硅（111）的图案化硅（110）层，侧壁取下面罩; 在图案化的硅（110）层上生长含SiGe的层; 并制造光电检测器。

43. 发明授权

US07157300B2 Fabrication of thin film germanium infrared sensor by bonding to silicon wafer 有权
标题翻译：通过粘合到硅晶片制造薄膜锗红外传感器
公开(公告)号：US07157300B2
公开(公告)日：2007-01-02
申请号：US10993533
申请日：2004-11-19
申请人： Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu , Douglas J. Tweet
发明人： Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu , Douglas J. Tweet
IPC分类号： H01L21/00
CPC分类号： H01L31/1804 , H01L21/187 , H01L21/76254 , H01L27/1443 , H01L31/02327 , H01L31/105 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.
摘要翻译：制造薄膜锗光电探测器的方法包括制备硅衬底; 在硅衬底上制造CMOS器件; 制备锗衬底; 准备每个基板的表面以进行接合; 将锗衬底结合到具有CMOS的硅衬底以形成结合结构; 从结合结构去除锗衬底的一部分; 在锗衬底中形成PIN二极管; 通过蚀刻去除锗层的一部分; 并完成锗光电检测器。

44. 发明授权

US07115945B2 Strained silicon fin structure 有权
公开(公告)号：US07115945B2
公开(公告)日：2006-10-03
申请号：US11327092
申请日：2006-01-06
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795 , H01L29/78687
摘要： Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

45. 发明授权

US07067430B2 Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction 失效
标题翻译：通过层压转移在绝缘体上制备松弛硅锗的方法
公开(公告)号：US07067430B2
公开(公告)日：2006-06-27
申请号：US10677005
申请日：2003-09-30
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/302
CPC分类号： H01L21/76254
摘要： A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 Å to 1 μm below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.
摘要翻译：在绝缘体上形成硅 - 锗层的方法包括在硅衬底上沉积硅 - 锗层以形成硅/硅 - 锗部分; 在硅 - 锗/硅界面之下的约500埃至1微米处将氢离子注入到硅衬底中; 将硅/硅锗部分接合到绝缘体基板上以形成对联体; 在第一热退火步骤中对联接件进行热退火以分离联接件; 图案化和蚀刻绝缘体上硅部分以去除部分硅和SiGe层; 蚀刻绝缘体上硅部分以除去剩余的硅层; 在第二退火步骤中对绝缘体上硅部分进行热退火以松弛SiGe层; 以及在SiGe层周围沉积一层应变硅。

46. 发明授权

US07045832B2 Vertical optical path structure for infrared photodetection 有权
标题翻译：用于红外光电检测的垂直光路结构
公开(公告)号：US07045832B2
公开(公告)日：2006-05-16
申请号：US10755567
申请日：2004-01-12
申请人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L29/732 , G01J5/20
CPC分类号： H01L31/105 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02639 , H01L27/14627 , H01L27/14643 , H01L31/02327 , H01L31/028 , H01L31/035281 , H01L31/108 , H01L31/109 , H01L31/1812 , Y02E10/547
摘要： Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.
摘要翻译：提供了SiGe垂直光路和用于选择性地形成用于IR光电检测的SiGe光路法线结构的方法。该方法包括：形成Si衬底表面; 形成Si特征，相对于诸如沟槽，通孔或支柱的Si衬底表面是正常的; 并且选择性地形成覆盖Si正常特征的SiGe光路。在一些方面，Si衬底表面形成第一平面，并且Si正常特征具有相对于Si衬底表面法线的壁（侧壁）和平行于第一平面的第二平面中的表面。然后，选择性地形成覆盖Si正常特征的SiGe光路包括形成覆盖正常特征壁的SiGe垂直光路。

47. 发明授权

US07045401B2 Strained silicon finFET device 有权
标题翻译：应变硅finFET器件
公开(公告)号：US07045401B2
公开(公告)日：2006-05-16
申请号：US10602436
申请日：2003-06-23
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
IPC分类号： H01L21/00 , H01L21/338
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795 , H01L29/78687
摘要： Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.
摘要翻译：公开了一种应变硅finFET器件，其具有双栅极finFET结构中的应变硅鳍通道。所公开的finFET器件是由用于抑制短沟道效应和增强驱动电流的自对准双栅极控制的硅鳍通道组成的双栅极MOSFET。所公开的finFET器件的硅鳍通道是应变硅鳍通道，包括沉积在具有不同晶格常数的种子鳍上的应变硅层，例如沉积在硅锗晶种鳍上的硅层或碳掺杂硅层沉积在硅种子翅片上。除了在finFET器件中固有的短沟道效应降低特性之外，硅层和种子鳍之间的晶格失配在所公开的finFET器件中产生应变硅鳍通道，以改善空穴和电子迁移率增强。

48. 发明授权

US06793731B2 Method for recrystallizing an amorphized silicon germanium film overlying silicon 失效
标题翻译：将硅非晶硅化硅膜再结晶的方法
公开(公告)号：US06793731B2
公开(公告)日：2004-09-21
申请号：US10098757
申请日：2002-03-13
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas J. Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas J. Tweet
IPC分类号： C30B3302
CPC分类号： H01L21/26506 , C30B1/023 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02513 , H01L21/02532 , H01L21/02694
摘要： A method is provided for forming a relaxed single-crystal silicon germanium film on a silicon substrate. Also provided is a film structure with a relaxed layer of graded silicon germanium on a silicon substrate. The method comprises: providing a silicon (Si) substrate with a top surface; growing a graded layer of strained single-crystal Si1−xGex having a bottom surface overlying the Si substrate top surface and a top surface, where x increases with the Si1−xGex layer thickness in the range between 0.03 and 0.5, wherein the Si1−xGex layer has a thickness in the range of 2500 Å to 5000 Å; implanting hydrogen ions; penetrating the Si substrate with the hydrogen ions a depth in the range of 300 Å to 1000 Å; implanting heavy ions, such as Si or Ge, into the Si1−xGex; in response to the heavy ion implantation, amorphizing a first region of the Si1−xGex layer adjacent the Si substrate; annealing; in response to the annealing, forming a hydrogen platelets layer between the Si substrate and the Si1−xGex layer; forming a silicon layer with a high density of hydrogen underlying the hydrogen platelets layer; and, forming a relaxed single-crystal Si1−xGex region, free of defects.
摘要翻译：提供了一种在硅衬底上形成松弛的单晶硅锗膜的方法。还提供了在硅衬底上具有缓和的渐变硅锗层的膜结构。该方法包括：提供具有顶表面的硅（Si）衬底; 生长具有覆盖Si衬底顶表面的底表面和顶表面的应变单晶Si1-xGex的分级层，其中x随着Si1-xGex层厚度在0.03和0.5之间的范围增加，其中Si1-xGex 层的厚度在2500埃至5000埃的范围内; 植入氢离子; 用氢离子穿透Si衬底，深度在300埃至1000埃的范围内; 将诸如Si或Ge的重离子注入到Si1-xGex中; 响应于重离子注入，使与Si衬底相邻的Si1-xGex层的第一区域非晶化; 退火; 响应于退火，在Si衬底和Si1-xGex层之间形成氢血小板层; 在氢薄膜层下形成具有高密度氢的硅层; 并形成松弛的单晶Si1-xGex区域，没有缺陷。

49. 发明申请

US20080280426A1 Gallium nitride-on-silicon interface 审中-公开
标题翻译：氮化镓在硅界面
公开(公告)号：US20080280426A1
公开(公告)日：2008-11-13
申请号：US11801210
申请日：2007-05-09
申请人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L29/739 , H01L21/20
CPC分类号： C30B29/406 , C30B25/183 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02642 , H01L21/02647 , H01L29/2003 , H01L29/267
摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.
摘要翻译：提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。该方法提供（111）Si衬底并且在压缩覆盖Si衬底上形成第一含铝（Al）的膜。在第一含Al膜中形成纳米柱孔，其暴露下面的Si衬底的区域。从暴露区域选择性地生长GaN层，覆盖第一含Al膜。使用横向纳米外延生长（LNEO）工艺生长GaN。重复上述过程，在压缩中形成第二含Al膜，在第二含Al膜中形成纳米柱孔，并选择性地生长第二GaN层。可以最初在低温下生长诸如Al 2 O 3 3，Si 1-x Ge x，InP，GaP，GaAs，AlN，AlGaN或GaN的膜材料。通过增加生长温度，可以在Si衬底上形成外延GaN的压缩层。

50. 发明授权

US06720258B2 Method of fabricating a nickel silicide on a substrate 有权
标题翻译：在衬底上制造硅化镍的方法
公开(公告)号：US06720258B2
公开(公告)日：2004-04-13
申请号：US10319313
申请日：2002-12-12
申请人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L29/456
摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.
摘要翻译：集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有任何取向偏好，从而形成均匀的硅化镍层。可以将镍硅化物退火以形成均匀的结晶二硅化镍。因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式