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41. 发明授权

US07436198B2 Test pattern of semiconductor device and test method using the same 失效
标题翻译：半导体器件的测试图案及使用其的测试方法
公开(公告)号：US07436198B2
公开(公告)日：2008-10-14
申请号：US11542589
申请日：2006-10-03
申请人： Jong-Hyun Lee
发明人： Jong-Hyun Lee
IPC分类号： G01R31/26
CPC分类号： G01R31/2884
摘要： There are provided a test pattern of a semiconductor device and a test method using the same. The test pattern of the semiconductor device includes a conductive pattern disposed on a semiconductor substrate, and the conductive pattern includes a plurality of line regions, which are aligned in parallel, and spaced at a uniform interval, and a plurality of connecting regions for connecting the plurality of line regions in a zigzag shape. The test pattern includes a plurality of transistors electrically switching first ends of the adjacent line regions corresponding to the connecting region, and each transistor includes a source region, which is electrically connected to one end of one of the adjacent line regions, and a drain region, which is electrically connected to one end of the other one of the adjacent line regions. Further, a transistor selecting part is electrically connected to gates of the plurality of transistors, for selecting one of the plurality of transistors or a combination thereof.
摘要翻译：提供半导体器件的测试图案和使用其的测试方法。半导体器件的测试图案包括布置在半导体衬底上的导电图案，并且导电图案包括平行排列并且间隔均匀的多个线区域，以及多个连接区域多个线形区域以Z字形形状。测试图案包括多个晶体管，其电连接与连接区域相对应的相邻线区域的第一端，并且每个晶体管包括电连接到一个相邻线区域的一端的源极区域和漏极区域，其电连接到另一个相邻线区域的一端。此外，晶体管选择部分电连接到多个晶体管的栅极，用于选择多个晶体管中的一个或其组合。

42. 发明授权

US07161374B2 Test pattern of semiconductor device and test method using the same 失效
标题翻译：半导体器件的测试图案及使用其的测试方法
公开(公告)号：US07161374B2
公开(公告)日：2007-01-09
申请号：US11028784
申请日：2005-01-04
申请人： Jong-Hyun Lee
发明人： Jong-Hyun Lee
IPC分类号： G01R31/26
CPC分类号： G01R31/2884
摘要： There are provided a test pattern of a semiconductor device and a test method using the same. The test pattern of the semiconductor device includes a conductive pattern disposed on a semiconductor substrate, and the conductive pattern includes a plurality of line regions, which are aligned in parallel, and spaced at a uniform interval, and a plurality of connecting regions for connecting the plurality of line regions in a zigzag shape. The test pattern includes a plurality of transistors electrically switching first ends of the adjacent line regions corresponding to the connecting region, and each transistor includes a source region, which is electrically connected to one end of one of the adjacent line regions, and a drain region, which is electrically connected to one end of the other one of the adjacent line regions. Further, a transistor selecting part is electrically connected to gates of the plurality of transistors, for selecting one of the plurality of transistors or a combination thereof.
摘要翻译：提供半导体器件的测试图案和使用其的测试方法。半导体器件的测试图案包括布置在半导体衬底上的导电图案，并且导电图案包括平行排列并且间隔均匀的多个线区域，以及多个连接区域多个线形区域以Z字形形状。测试图案包括多个晶体管，其电连接与连接区域相对应的相邻线区域的第一端，并且每个晶体管包括电连接到一个相邻线区域的一端的源极区域和漏极区域，其电连接到另一个相邻线区域的一端。此外，晶体管选择部分电连接到多个晶体管的栅极，用于选择多个晶体管中的一个或其组合。

43. 发明申请

US20060175668A1 Analytic structure for failure analysis of semiconductor device 有权
标题翻译：半导体器件故障分析分析结构
公开(公告)号：US20060175668A1
公开(公告)日：2006-08-10
申请号：US11346678
申请日：2006-02-03
申请人： Ki-Am Lee , Jong-Hyun Lee
发明人： Ki-Am Lee , Jong-Hyun Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/1104 , H01L27/11
摘要： In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors, each comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns. A first number of layers of the multiple layered metal patterns and multiple layered plugs is different in one of the analytic regions than a second number of layers of the multiple layered metal patterns and multiple layered plugs in another one of the analytic regions.
摘要翻译：在用于半导体器件的故障分析的分析结构中，多个分析区域布置在半导体衬底的区域中。在每个分析区域中布置有具有阵列结构的多个半导体晶体管。多个互连结构连接半导体晶体管，每个半导体晶体管包括多层金属图案和插入在多层金属图案之间的多个分层插塞。在多个分层金属图案和多个分层塞子的第一层中，一个分析区域中的多层金属图案的第二数量层和另一个分析区域中的多个分层塞子是不同的。

44. 发明授权

US06928243B2 Optical performance monitoring apparatus for a WDM optical communication system 有权
标题翻译：一种用于WDM光通信系统的光学性能监测装置
公开(公告)号：US06928243B2
公开(公告)日：2005-08-09
申请号：US09736267
申请日：2000-12-15
申请人： Ji-Wook Youn , Sung-Un Lee , Kwang-Joon Kim , Jong-Hyun Lee
发明人： Ji-Wook Youn , Sung-Un Lee , Kwang-Joon Kim , Jong-Hyun Lee
IPC分类号： H04B10/077 , H04B10/079 , H04J14/02 , H04B10/08
CPC分类号： H04B10/077 , H04B10/07955 , H04J14/02
摘要： The optical performance monitoring apparatus includes a first optical distributor for distributing a WDM optical signal branched from an optical transmission line, a plurality of wavelength selectors, each for selecting a predetermined wavelength optical signal from the optical signal distributed, a plurality of first optical detectors, each for detecting power of the predetermined wavelength optical signal for a corresponding one of channels selected by the wavelength selectors; and a signal processor for measuring the power for each channel of the WDM optical signal, a total ASE noise power, and an optical signal-to-noise ratio for each channel from the digital value.
摘要翻译：光学性能监视装置包括用于分配从光传输线分支的WDM光信号的第一光分配器，用于从分配的光信号中选择预定波长光信号的多个波长选择器，多个第一光检测器，每个用于检测由波长选择器选择的相应一个通道的预定波长光信号的功率; 以及信号处理器，用于从数字值测量每个信道的WDM光信号的每个信道的功率，总ASE噪声功率和每个信道的光信噪比。

45. 发明申请

US20050156617A1 Test pattern of semiconductor device and test method using the same 失效
标题翻译：半导体器件的测试图案及使用其的测试方法
公开(公告)号：US20050156617A1
公开(公告)日：2005-07-21
申请号：US11028784
申请日：2005-01-04
申请人： Jong-Hyun Lee
发明人： Jong-Hyun Lee
IPC分类号： G01R31/02 , G01R31/28 , H01L21/66 , H01L21/822 , H01L27/04 , G01R31/26
CPC分类号： G01R31/2884
摘要： There are provided a test pattern of a semiconductor device and a test method using the same. The test pattern of the semiconductor device includes a conductive pattern disposed on a semiconductor substrate, and the conductive pattern includes a plurality of line regions, which are aligned in parallel, and spaced at a uniform interval, and a plurality of connecting regions for connecting the plurality of line regions in a zigzag shape. The test pattern includes a plurality of transistors electrically switching first ends of the adjacent line regions corresponding to the connecting region, and each transistor includes a source region, which is electrically connected to one end of one of the adjacent line regions, and a drain region, which is electrically connected to one end of the other one of the adjacent line regions. Further, a transistor selecting part is electrically connected to gates of the plurality of transistors, for selecting one of the plurality of transistors or a combination thereof.
摘要翻译：提供半导体器件的测试图案和使用其的测试方法。半导体器件的测试图案包括布置在半导体衬底上的导电图案，并且导电图案包括平行排列并且间隔均匀的多个线区域，以及多个连接区域多个线形区域以Z字形形状。测试图案包括多个晶体管，其电连接与连接区域相对应的相邻线区域的第一端，并且每个晶体管包括电连接到一个相邻线区域的一端的源极区域和漏极区域，其电连接到另一个相邻线区域的一端。此外，晶体管选择部分电连接到多个晶体管的栅极，用于选择多个晶体管中的一个或其组合。

46. 发明授权

US06800549B2 Method of fabricating semiconductor device including forming contact hole with anisotropic and isotropic etching and forming discontinuous barrier layer 失效
标题翻译：制造半导体器件的方法包括：形成具有各向异性和各向同性蚀刻的接触孔并形成不连续的阻挡层
公开(公告)号：US06800549B2
公开(公告)日：2004-10-05
申请号：US10705480
申请日：2003-11-10
申请人： Jong-Hyun Lee
发明人： Jong-Hyun Lee
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76868 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device with a via contact including a barrier metal layer and a method for fabricating the same, a lower metal interconnection is formed over a substrate. An ILD is formed on the lower metal interconnection and has a lower barrier layer and an upper barrier layer that have an etch selectivity with respect to each other. An upper metal interconnection is formed over the ILD and is separated from the lower metal interconnection by the ILD. A via contact plug penetrates the ILD to connect the lower and upper metal interconnections. The via contact plug is formed such that a portion crossing the lower barrier layer is formed to have a greater width as compared to a portion crossing the upper barrier layer. The barrier metal layer, which is formed to encompass sidewalls and a bottom of an inner metal layer of the via contact plug, forms a discontinuous part which does not exist at the portion crossing the lower barrier layer. Thus, the inner metal layer of the contact plug is in direct contact with the lower metal interconnection. The upper and lower barrier layers are layers that serve as a barrier to copper, such as a silicon nitride layer or silicon carbide layer. However, the upper and lower barrier layers are composed of different material layers so as to have etch selectivity with respect to each other.
摘要翻译：在具有包括阻挡金属层的通孔接触的半导体器件及其制造方法中，在衬底上形成下部金属互连。在下金属互连上形成有ILD，并且具有相对于彼此具有蚀刻选择性的下阻挡层和上阻挡层。在ILD上形成上金属互连，并且通过ILD与下金属互连分离。通孔接触插头穿透ILD以连接下部和上部金属互连。通孔接触插塞形成为与穿过上阻挡层的部分相比，与下阻挡层交叉的部分形成为具有更大的宽度。形成为包围通孔接触塞的内金属层的侧壁和底部的阻挡金属层在与下阻挡层交叉的部分形成不存在的不连续部分。因此，接触插塞的内金属层与下金属互连直接接触。上阻挡层和下阻挡层是用作铜的屏障的层，例如氮化硅层或碳化硅层。然而，上阻挡层和下阻挡层由不同的材料层组成，以便相对于彼此具有蚀刻选择性。

47. 发明授权

US06570698B2 Apparatus and method for modulating optical intensity with amplitude noise suppressed by using linear optical modulator 有权
公开(公告)号：US06570698B2
公开(公告)日：2003-05-27
申请号：US09750072
申请日：2000-12-29
申请人： Bong-Kyu Kim , Kwang-Joon Kim , Jong-Hyun Lee , Seung-Il Myong
发明人： Bong-Kyu Kim , Kwang-Joon Kim , Jong-Hyun Lee , Seung-Il Myong
IPC分类号： G02F101
CPC分类号： G02F1/0123 , H04B10/5051 , H04B10/50575 , H04B10/58
摘要： An apparatus and a method for modulating the optical intensity, with the noises suppressed by using a linear optical modulator, are disclosed, so that the characteristics of signals transmitted from an optical communication system can be improved, and that the resolution of the measured physical quantities can be improved in an optical measuring instrument. The method is carried out in the following manner. That is, the magnitude of frequency is measured by utilizing pilot signals and electrical signals to transfer negatively fed-back signals to an optical intensity modulator. The phase is delayed by generating pilot signals so as to suppress an amplitude noise from the pilot signal caused by nonlinear modulation at the optical intensity modulator. A linear modulation is carried out on the phase-delayed signals and on optical signals from an external source to provide a linear component. The bias voltage is adjusted in accordance with the negatively fed-back signals, and an optical intensity modulation is carried out on the linearly modulated signals and on the added signals, the added signals having been formed by combining the data signals and the pilot signals.

48. 发明授权

US09005823B2 Electrolyte for rechargeable lithium battery and rechargeable lithium battery including the same 有权
标题翻译：可充电锂电池和可充电锂电池的电解液包括相同
公开(公告)号：US09005823B2
公开(公告)日：2015-04-14
申请号：US13241133
申请日：2011-09-22
申请人： Duck-Chul Hwang , Eun-Gi Shim , Jong-Hyun Lee , Jong-Su Kim , Young-Min Kim
发明人： Duck-Chul Hwang , Eun-Gi Shim , Jong-Hyun Lee , Jong-Su Kim , Young-Min Kim
IPC分类号： H01M6/16 , H01M4/13 , H01M4/58 , H01M10/0567 , H01M4/36 , H01M4/38 , H01M4/48 , H01M4/587 , H01M10/052
CPC分类号： H01M10/0567 , H01M4/362 , H01M4/386 , H01M4/483 , H01M4/587 , H01M10/052
摘要： An electrolyte for a rechargeable lithium battery includes a non-aqueous organic solvent, a lithium salt, and an additive. The additive includes a gamma butyrolactone compound substituted with at least one F atom at the α-position.
摘要翻译：用于可再充电锂电池的电解质包括非水有机溶剂，锂盐和添加剂。添加剂包括在α-位被至少一个F原子取代的γ-丁内酯化合物。

49. 发明授权

US09001101B2 Liquid crystal display device and method of driving the same 有权
标题翻译：液晶显示装置及其驱动方法
公开(公告)号：US09001101B2
公开(公告)日：2015-04-07
申请号：US13338819
申请日：2011-12-28
申请人： Kwang-Pyo Hong , Jong-Hyun Lee
发明人： Kwang-Pyo Hong , Jong-Hyun Lee
IPC分类号： G09G5/00 , G09G3/36 , G02F1/1362
CPC分类号： G02F1/136213 , G02F2201/121 , G09G3/3614 , G09G3/3648 , G09G2300/0426
摘要： A liquid crystal display device includes: a plurality of gate and data lines crossing each other on a substrate to define a plurality of pixels; a thin film transistor in each pixel region and connected to the corresponding gate and data lines; a pixel electrode in each pixel region and connected to a drain electrode of the thin film transistor; and an opposing electrode that forms a capacitor in each pixel along with the pixel electrode, wherein the pixel electrode of a pixel at a nth row line and a mth column line is connected to the opposing electrode of a neighboring pixel along the mth column line or along the nth row line.
摘要翻译：液晶显示装置包括：在基板上彼此交叉的多个栅极和数据线，以限定多个像素; 每个像素区域中的薄膜晶体管，并连接到相应的栅极和数据线; 每个像素区域中的像素电极并连接到薄膜晶体管的漏电极; 以及与像素电极一起在每个像素中形成电容器的对置电极，其中第n行线和第m列线上的像素的像素电极沿着第m列线连接到相邻像素的相对电极，或沿第n行。

50. 发明申请

US20120248437A1 Semiconductor Device And Test Method For Semiconductor Device 审中-公开
标题翻译：半导体器件半导体器件及测试方法
公开(公告)号：US20120248437A1
公开(公告)日：2012-10-04
申请号：US13176855
申请日：2011-07-06
申请人： Jong-Hyun Lee , Ki-Heung Park
发明人： Jong-Hyun Lee , Ki-Heung Park
IPC分类号： H01L23/52
CPC分类号： H01L22/34
摘要： A semiconductor device includes a first metal pattern formed on a first metal level. The first metal pattern has a ‘U’ shaped first curved portion. A second metal pattern is formed on the first metal level. The second metal pattern has a ‘U’ shaped second curved portion facing the first curved portion. A via structure is electrically connected to one of the first metal pattern and the second metal pattern. A third metal pattern is formed on a second metal level different from the first metal level and electrically connected to the via structure.
摘要翻译：半导体器件包括形成在第一金属层上的第一金属图案。第一金属图案具有U形的第一弯曲部分。在第一金属层上形成第二金属图案。第二金属图案具有面向第一弯曲部分的U形第二弯曲部分。通孔结构电连接到第一金属图案和第二金属图案之一。第三金属图案形成在不同于第一金属层的第二金属层上，并电连接到通孔结构。

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