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41. 发明授权

US06256653B1 Multi-function bipartite look-up table 失效
标题翻译：多功能二分查询表
公开(公告)号：US06256653B1
公开(公告)日：2001-07-03
申请号：US09015084
申请日：1998-01-29
申请人： Norbert Juffa , Stuart F. Oberman
发明人： Norbert Juffa , Stuart F. Oberman
IPC分类号： G06F102
CPC分类号： G06F7/53 , G06F7/483 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/509 , G06F7/5338 , G06F7/5443 , G06F9/30014 , G06F9/30021 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F17/16 , G06F2207/3828 , H03M7/24
摘要： A multi-function look-up table for determining output values for predetermined ranges of a first mathematical function and a second mathematical function. In one embodiment, the multi-function look-up table is a bipartite look-up table including a first plurality of storage locations and a second plurality of storage locations. The first plurality of storage locations store base values for the first and second mathematical functions. Each base value is an output value (for either the first or second function) corresponding to an input region which includes the look-up table input value. The second plurality of storage locations, on the other hand, store difference values for both the first and second mathematical functions. These difference values are used for linear interpolation in conjunction with a corresponding base value in order to generate a look-up table output value. The multi-function look-up table further includes an address control unit coupled to receive a first input value and a signal which indicates whether an output value is to be generated for the first or second mathematical function. The address control unit then generates a first address value from these signals which is in turn conveyed to the first and second plurality of storage locations. In response to receiving the first address value, the first and second plurality of storage locations are configured to output a first base value and a first difference value, respectively. The first base value and first difference value are then conveyed to an output unit configured to generate a look-up table output value from the two values.
摘要翻译：一种用于确定第一数学函数和第二数学函数的预定范围的输出值的多功能查找表。在一个实施例中，多功能查找表是包括第一多个存储位置和第二多个存储位置的二分查找表。第一多个存储位置存储第一和第二数学函数的基值。每个基值是对应于包括查找表输入值的输入区域的输出值（对于第一或第二函数）。另一方面，第二多个存储位置存储第一和第二数学函数的差值。这些差值用于与对应的基值相结合的线性插值，以产生查询表输出值。多功能查找表还包括地址控制单元，其被耦合以接收第一输入值和指示是否为第一或第二数学函数生成输出值的信号。地址控制单元然后从这些信号产生一个第一地址值，该第一地址值又被传送到第一和第二多个存储位置。响应于接收到第一地址值，第一和第二多个存储位置被配置为分别输出第一基值和第一差值。然后将第一基值和第一差分值传送到被配置为从两个值生成查找表输出值的输出单元。

42. 发明授权

US6144980A Method and apparatus for performing multiple types of multiplication including signed and unsigned multiplication 失效
标题翻译：用于执行包括有符号和无符号乘法的多种类型的乘法的方法和装置
公开(公告)号：US6144980A
公开(公告)日：2000-11-07
申请号：US14454
申请日：1998-01-28
申请人： Stuart F. Oberman
发明人： Stuart F. Oberman
IPC分类号： G06F7/52 , G06F7/533 , G06F7/544 , G06F9/318 , G06F9/38 , G06F17/16
CPC分类号： G06F7/53 , G06F17/16 , G06F7/5443 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F2207/3828 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/5338
摘要： A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and may include a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand's most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, the adder is configured to sum them and output the results, which may be signed or unsigned. When a vector multiplication is performed, the multiplier is configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.
摘要翻译：公开了能够执行有符号和无符号标量和矢量乘法的乘法器。乘法器被配置为用于微处理器，并且可以包括部分乘积发生器，选择逻辑单元和加法器。乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。乘法器还被配置为接收指示是否要执行带符号或无符号乘法的第一控制信号，以及指示是否执行向量乘法的第二控制信号。乘法器被配置为基于每个操作数的最高有效位和控制信号来计算乘数的有效符号和被乘数操作数。然后，有效符号可以被部分乘积生成单元和选择逻辑用于根据布斯算法创建和选择多个部分乘积。一旦创建并选择了部分产品，加法器被配置为对它们进行求和并输出结果，这可能是有符号或无符号的。当执行向量乘法时，乘法器被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。

43. 发明授权

US6085212A Efficient method for performing close path subtraction in a floating point arithmetic unit 失效
标题翻译：在浮点运算单元中执行近似路径减法的高效方法
公开(公告)号：US6085212A
公开(公告)日：2000-07-04
申请号：US49863
申请日：1998-03-27
申请人： Stuart F. Oberman
发明人： Stuart F. Oberman
IPC分类号： G06F7/57 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , H03M7/24 , G06F7/42
CPC分类号： G06F9/3017 , G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/3804 , G06F9/3885 , H03M7/24
摘要： An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far data path is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path, conversely, is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close data path may include an adder unit configured to generate a first and second output value. The first output value is equal to the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. The two output values are conveyed to a multiplexer unit, which selects one of the output values as a preliminary subtraction result. Selection of the first or second output value in the close data path effectuates the round-to-nearest operation for the output of the adder. The execution unit may also be configured to perform floating point-to-integer and integer-to-floating point conversions.
摘要翻译：优化的多媒体执行单元被配置为执行矢量的浮点和整数指令。执行单元可以包括具有远近数据路径的加法/减法流水线。远数据路径被配置为处理有效的加法运算，以及具有大于1的绝对指数差的操作数的有效减法运算。相反地，关闭数据路径被配置为处理具有小于或等于1的绝对指数差的操作数的有效减法操作。关闭数据路径可以包括被配置为生成第一和第二输出值的加法器单元。第一个输出值等于第一个输入操作数加第二个输入操作数的反转版本，而第二个输出值等于第一个输出值加一。两个输出值被传送到多路复用器单元，其选择输出值之一作为初步减法结果。关闭数据路径中的第一或第二输出值的选择为加法器的输出实现了舍入到最近的运算。执行单元还可以被配置为执行浮点到整数和整数到浮点转换。

44. 发明授权

US08860741B1 Graphics processor with memory management unit and cache coherent link 有权
标题翻译：具有内存管理单元和缓存一致链接的图形处理器
公开(公告)号：US08860741B1
公开(公告)日：2014-10-14
申请号：US11608436
申请日：2006-12-08
申请人： Norbert Juffa , Stuart F. Oberman
发明人： Norbert Juffa , Stuart F. Oberman
IPC分类号： G09G5/36
CPC分类号： G09G5/36 , G06F9/50 , G06F12/0831 , G06F2212/302 , G09G5/363
摘要： In contrast to a conventional computing system in which the graphics processor (graphics processing unit or GPU) is treated as a slave to one or several CPUs, systems and methods are provided that allow the GPU to be treated as a central processing unit (CPU) from the perspective of the operating system. The GPU can access a memory space shared by other CPUs in the computing system. Caches utilized by the GPU may be coherent with caches utilized by other CPUs in the computing system. The GPU may share execution of general-purpose computations with other CPUs in the computing system.
摘要翻译：与将图形处理器（图形处理单元或GPU）视为一个或多个CPU的从属设备的常规计算系统相反，提供允许GPU被视为中央处理单元（CPU）的系统和方法，从操作系统的角度。 GPU可以访问计算系统中其他CPU共享的内存空间。 GPU使用的高速缓存可能与计算系统中其他CPU所使用的高速缓存一致。 GPU可能与计算系统中的其他CPU共享通用计算的执行。

45. 发明授权

US07809852B2 High jitter scheduling of interleaved frames in an arbitrated loop 失效
标题翻译：仲裁循环中交错帧的高抖动调度
公开(公告)号：US07809852B2
公开(公告)日：2010-10-05
申请号：US10152763
申请日：2002-05-22
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： G06F13/00
CPC分类号： H04L47/6215 , H04L12/433 , H04L47/22 , H04L47/283 , H04L47/50 , H04L47/6225 , H04L49/357
摘要： A system and method for converting low-jitter, interleaved frame traffic, such as that generated in an IP network, to high jitter traffic to improve the utilization of bandwidth on arbitrated loops such as Fibre Channel Arbitrated Loops. Embodiments of a high jitter scheduling algorithm may be used in devices such as network switches that interface an arbitrated loop with an IP network that carries low-jitter traffic. The high jitter algorithm may use a separate queue for each device on the arbitrated loop, or alternatively may use one queue for two or more devices. Incoming frames are distributed among the queues based upon each frame's destination device. The scheduling algorithm may then service the queues and forward queued frames to the devices from the queues. In one embodiment, the queues are serviced in a round-robin fashion. In one embodiment, each queue may be serviced for a programmed limit.
摘要翻译：将诸如IP网络中生成的低抖动交织帧流量转换为高抖动流量以提高诸如光纤通道仲裁环路之类的仲裁环路上的带宽利用率的系统和方法。高抖动调度算法的实施例可以用于诸如将仲裁环路与承载低抖动流量的IP网络相连接的网络交换机的设备。高抖动算法可以对仲裁环路上的每个设备使用单独的队列，或者可以为两个或更多个设备使用一个队列。基于每个帧的目的地设备，进入的帧被分配在队列之间。然后，调度算法可以对队列进行服务并将排队的帧从队列转发到设备。在一个实施例中，队列以循环方式服务。在一个实施例中，每个队列可以被服务于编程限制。

46. 发明授权

US07659893B1 Method and apparatus to ensure consistency of depth values computed in different sections of a graphics processor 失效
标题翻译：确保在图形处理器的不同部分计算的深度值的一致性的方法和装置
公开(公告)号：US07659893B1
公开(公告)日：2010-02-09
申请号：US11538002
申请日：2006-10-02
申请人： Stuart F. Oberman , Steven E. Molnar , Alexander L. Minkin , Peter B. Holmqvist
发明人： Stuart F. Oberman , Steven E. Molnar , Alexander L. Minkin , Peter B. Holmqvist
IPC分类号： G06T15/40
CPC分类号： G06T15/405 , G06T15/005 , G06T2200/28
摘要： At least two different processing sections in a graphics processors compute Z coordinates for a sample location from a compressed Z representation. The processors are designed to ensure that Z coordinates computed in any unit in the processor are identical. In one embodiment, the respective arithmetic circuits included in each processing section that computes Z coordinates are “bit-identical,” meaning that, for any input planar Z representation and coordinates, the output Z coordinates produced by the circuits are identical to each other.
摘要翻译：图形处理器中的至少两个不同的处理部分从压缩的Z表示中计算样本位置的Z坐标。处理器被设计为确保在处理器中的任何单元中计算的Z坐标是相同的。在一个实施例中，计算Z坐标的每个处理部分中包括的相应运算电路是“位相同”，这意味着对于任何输入的平面Z表示和坐标，由电路产生的输出Z坐标彼此相同。

47. 发明授权

US07227841B2 Packet input thresholding for resource distribution in a network switch 失效
标题翻译：网络交换机资源分配的分组输入阈值
公开(公告)号：US07227841B2
公开(公告)日：2007-06-05
申请号：US10144081
申请日：2002-05-13
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： G01R31/08
CPC分类号： H04L47/32 , H04L47/29 , H04L47/50 , H04L49/103 , H04L49/108 , H04L49/30 , H04L49/90 , H04L49/901 , H04L49/9036 , H04L49/9094 , H04L2012/5681
摘要： A system and method for input thresholding packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the network switch may be assigned to one of a plurality of threshold groups and to one of a plurality of flows within the threshold group. In one embodiment, each threshold group may be divided into a plurality of levels of operation. As resources are allocated or freed by the threshold group, the threshold group may dynamically move up or down in the levels of operation. Within each level, one or more different values may be used as level boundaries and resource limits for flows within the threshold group. In one embodiment, programmable registers may be used to store these values.
摘要翻译：一种用于在网络交换机中输入阈值分组的系统和方法。网络交换机可以包括多个输入端口，多个输出端口以及通过数据传输逻辑耦合到输入端口和输出端口的共享随机存取存储器。可以将进入网络交换机的分组分配给多个阈值组中的一个和阈值组内的多个流中的一个。在一个实施例中，每个阈值组可被划分成多个操作级别。当资源由阈值组分配或释放时，阈值组可以在操作级别上动态上移或下移。在每个级别内，可以使用一个或多个不同的值作为阈值组内的流的级别边界和资源限制。在一个实施例中，可以使用可编程寄存器来存储这些值。

48. 发明授权

US07215680B2 Method and apparatus for scheduling packet flow on a fibre channel arbitrated loop 失效
标题翻译：用于在光纤信道仲裁环路上调度分组流的方法和装置
公开(公告)号：US07215680B2
公开(公告)日：2007-05-08
申请号：US10144187
申请日：2002-05-13
申请人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
发明人： Rodney N. Mullendore , Stuart F. Oberman , Anil Mehta , Keith Schakel , Kamran Malik
IPC分类号： H04L12/56
CPC分类号： H04L47/2433 , H04L47/50 , H04L47/56 , H04L47/6225 , H04L49/205 , H04L49/254 , H04L49/3018 , H04L49/351 , H04L49/357 , H04L67/1097 , H04L69/329
摘要： A system and method for enabling a network switch to transmit queued packets to a device when opened by the device, and thus to utilize the Fibre Channel Arbitrated Loop (FC-AL) in full-duplex mode when possible. The switch may include a plurality of queues each associated with a device on the FC-AL for queuing incoming packets for the device. The switch may determine a next non-empty queue, open the device associated with the queue, and send packets to the device. The device may send packets to the switch concurrently with receiving packets from the switch, thus utilizing the FC-AL in full-duplex mode. When a device opens the switch to transmit packets to the switch, the switch may determine if there are packets for the device in the queue and, if so, send packets to the device concurrently with receiving packets from the device, thus utilizing the FC-AL in full-duplex mode.
摘要翻译：一种用于使网络交换机能够在设备打开时将排队的分组传送到设备的系统和方法，并且因此在可能的情况下以全双工模式利用光纤通道仲裁环路（FC-AL）。交换机可以包括多个队列，每个队列与FC-AL上的设备相关联，用于对用于设备的输入分组进行排队。交换机可以确定下一个非空队列，打开与队列关联的设备，并将数据包发送到设备。设备可以同时从交换机接收数据包发送数据包，从而在全双工模式下利用FC-AL。当设备打开交换机向交换机发送数据包时，交换机可以确定队列中是否存在设备的数据包，如果是，则从设备接收数据包并发发送数据包，从而利用FC- AL在全双工模式。

49. 发明授权

US06487653B1 Method and apparatus for denormal load handling 有权
标题翻译：用于异常负载处理的方法和装置
公开(公告)号：US06487653B1
公开(公告)日：2002-11-26
申请号：US09383138
申请日：1999-08-25
申请人： Stuart F. Oberman , Stephan G. Meier , Jeffrey E. Trull
发明人： Stuart F. Oberman , Stephan G. Meier , Jeffrey E. Trull
IPC分类号： G06F738
CPC分类号： G06F9/3836 , G06F7/49905 , G06F9/30025 , G06F9/30043 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3873
摘要： A microprocessor configured to dynamically switch its floating point load pipeline length from one stage in length to more than one stage in length is disclosed. The microprocessor may perform normal loads and detect denormal loads in a single clock cycle. The microprocessor temporarily stores each scheduled floating point instruction in a reissue buffer for at least one clock cycle. When a denormal load instruction is detected, the microprocessor is configured to add one or more stages to the floating point load pipeline to allow the denormal value to complete the conversion to an internal format. The longer pipeline is then used for all loads that follow the denormal load until there is an idle clock cycle or an abort occurs. At that point, the pipeline reverts back to its original shorter state. In addition, the microprocessor may be configured to cancel instructions scheduled assuming the denormal load would take only one clock cycle to complete. The canceled instruction is then “replayed” during a later clock cycle from the reissue buffer. A method for performing denormal loads and a computer system are also disclosed.
摘要翻译：公开了一种被配置为将其浮点负载流水线长度从一个阶段长度动态地切换到多于一个阶段的微处理器。微处理器可以在单个时钟周期内执行正常负载并检测异常负载。微处理器将至少一个时钟周期的每个调度的浮点指令临时存储在再发行缓冲器中。当检测到非正常加载指令时，微处理器被配置为向浮点加载流水线添加一个或多个级，以允许异常值完成到内部格式的转换。然后，较长的流水线将用于跟随异常负载的所有负载，直到发生空闲时钟周期或中止发生。在这一点上，管道恢复到原来的较短状态。此外，微处理器可以被配置为取消预定的指令，假设正常负载仅需要一个时钟周期来完成。然后在从重新发行缓冲区的较后时钟周期内“取消”取消的指令。还公开了一种用于执行异常负载的方法和计算机系统。

50. 发明授权

US06487575B1 Early completion of iterative division 有权
标题翻译：提前完成迭代划分
公开(公告)号：US06487575B1
公开(公告)日：2002-11-26
申请号：US09385188
申请日：1999-08-30
申请人： Stuart F. Oberman
发明人： Stuart F. Oberman
IPC分类号： G06F738
CPC分类号： G06F7/4873 , G06F7/49926
摘要： A multiplier configured to execute division and square root operations by executing iterative multiplication operations is disclosed. The multiplier is configured to complete divide-by-two and zero dividend instructions in fewer clock cycles by detecting them before or during the first iteration and then performing an exponent adjustment and rounding the result to the desired precision. A system and method for rapidly executing divide-by-two and zero dividend instructions within the context of a multiplier that executes division and square root instructions using iterative multiplication are also disclosed.
摘要翻译：被配置为通过执行迭代乘法运算执行除法和平方根操作的乘法器被公开。乘法器被配置为通过在第一次迭代之前或期间检测它们来在更短的时钟周期内完成二分频和零除数指令，然后执行指数调整并将结果舍入到期望的精度。还公开了一种用于在使用迭代乘法执行除法和平方根指令的乘法器的上下文中快速执行二分频和零除数指令的系统和方法。

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