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41. 发明授权

US5894569A Method and system for back-end gathering of store instructions within a data-processing system 失效
标题翻译：在数据处理系统中后台收集存储指令的方法和系统
公开(公告)号：US5894569A
公开(公告)日：1999-04-13
申请号：US839480
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F9/312 , G06F9/38 , G06F7/00
CPC分类号： G06F9/30043 , G06F9/3824
摘要： A method and system for back-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, a store queue within a data-processing system includes a front-end queue and a back-end queue. A multiple of entries is provided in the back-end queue, and each entry includes an address field, a byte-count field, and a data field. A determination is first made as to whether or not a data field of a last entry of the back-end queue is completely filled. In response to a determination that the data field of the last entry of the back-end queue is not completely filled, another determination is made as to whether or not an address for a store instruction in a subsequent entry is equal to an address for a store instruction in the last entry plus a byte count in the last entry. In response to a determination that the address for a store instruction in a subsequent entry is equal to the address for a store instruction in the last entry plus the byte count in the last entry, the two store instructions are combined into one bus transfer.
摘要翻译：公开了一种用于处理器内存储指令后端收集的方法和系统。根据本发明的方法和系统，数据处理系统内的存储队列包括前端队列和后端队列。在后端队列中提供多个条目，并且每个条目包括地址字段，字节计数字段和数据字段。首先确定后端队列的最后一个条目的数据字段是否被完全填充。响应于后端队列的最后条目的数据字段未被完全填写的确定，另外确定后续条目中存储指令的地址是否等于在最后一个条目中存储指令加上最后一个条目中的字节数。响应于确定后续条目中存储指令的地址等于最后一个条目中的存储指令的地址加上最后一个条目中的字节计数，两个存储指令被组合成一个总线传输。

42. 发明授权

US06662216B1 Fixed bus tags for SMP buses 失效
标题翻译：用于SMP总线的固定总线标签
公开(公告)号：US06662216B1
公开(公告)日：2003-12-09
申请号：US08839478
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明的第一方面，提供一种数据处理系统，其包括多个设备耦合到的通信网络。多个设备中的第一个包括多个请求者（或队列），每个请求者（或队列）被永久地分配多个唯一标签中的相应的一个。响应于第一设备内的请求者的通信请求，分配给请求者的标签与所请求的通信事务一起在通信网络上发送。根据本发明的第二方面，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

43. 发明授权

US06507880B1 Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens 失效
标题翻译：总线协议，总线主机和总线监听器，用于执行使用多个令牌的全局操作
公开(公告)号：US06507880B1
公开(公告)日：2003-01-14
申请号：US09435927
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits one of a plurality of tokens required to complete the global operation and identifies the global operation to be processed with the token, if granted. Bus snoopers contain a number of snooper queues for global operations equal to the number of global operation tokens employed within the multiprocessor system. A bus snooper, upon detecting a combined token and operation request, begins speculatively processing the operation if the snooper is not already busy. Before completing the operation, the snooper watches for a combined response with a token number acknowledging either the combined request or a subsequent token request from the same processor, which indicates that the originating bus master has been granted a token for completing a global operation. Otherwise, a combined response acknowledging an operation request containing the token number implies release of the granted token.
摘要翻译：响应于启动全局操作的需要，多处理器系统内的总线主机在耦合到总线主机的总线上发出组合的令牌和操作请求。组合的令牌和操作请求请求完成全局操作所需的多个令牌中的一个令牌，并且如果被授权则标识要用令牌处理的全局操作。总线侦听器包含多个用于全局操作的侦听队列，等于在多处理器系统中使用的全局操作令牌的数量。一旦检测到组合的令牌和操作请求，总线侦听器开始推测性地处理该操作，如果该侦听器尚未忙。在完成操作之前，窥探者使用令牌号来识别来自同一处理器的组合请求或后续令牌请求的组合响应，其指示始发总线主机已经被授予用于完成全局操作的令牌。否则，确认包含令牌号的操作请求的组合响应意味着释放所授予的令牌。

44. 发明授权

US06502171B1 Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data 失效
标题翻译：具有组合侦听响应的多处理器系统总线显式通知窥探者围绕数据
公开(公告)号：US06502171B1
公开(公告)日：2002-12-31
申请号：US09368231
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same level as the storage device initiating the combined operation to allocate and store either the cast out or target data. A horizontal storage device having available space—i.e., an invalid or modified data element in a congruence class for the victim—stores either the target or the cast out data for subsequent access by an intervention. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.
摘要翻译：组合响应逻辑在取消组合操作包括与丢弃相关的数据访问的组合操作时，明确指示与启动组合操作的存储设备处于同一级别的水平存储设备，以分配和存储任务或目标数据。具有可用空间的水平存储设备（即，用于受害者的同余类中的无效或修改的数据元素）存储目标或丢弃数据以供随后的干预访问。取消投票，从而延迟与将丢弃的受害者写入系统内存相关的任何延迟，同时最大限度地利用可用存储在数据访问延迟中具有可接受的折中。

45. 发明授权

US06502168B1 Cache having virtual cache controller queues 失效
标题翻译：缓存具有虚拟缓存控制器队列
公开(公告)号：US06502168B1
公开(公告)日：2002-12-31
申请号：US09404028
申请日：1999-09-23
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

46. 发明授权

US06430683B1 Processor and method for just-in-time delivery of load data via time dependency field 失效
标题翻译：通过时间依赖性字段即时传送负载数据的处理器和方法
公开(公告)号：US06430683B1
公开(公告)日：2002-08-06
申请号：US09344023
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3838 , G06F12/0855 , G06F12/0859 , G06F13/4217
摘要： A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency bit field of a load instruction to create a Distance of Dependency (DoD) bit field. The DoD bit field holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by the DoD bit field. In the preferred embodiment, an acknowledgement is sent to the processing unit when the time specified is available in the RTOQ.
摘要翻译：用于加载指令的时间执行的系统。更具体地，该系统实现了由加载指令请求的数据的及时传送。该系统由处理器，具有对应的L1高速缓存控制器的L1数据高速缓存器和指令处理器组成。指令处理器操纵负载指令的架构化时间依赖性位字段以创建依赖距离（DoD）位字段。 DoD位域保持相对依赖性值，该值用于对L1高速缓存控制器的相对时间排序队列（RTOQ）中的加载指令进行排序。加载指令在特定时间从RTOQ发送到L1数据高速缓存，以便在DoD位字段指定的时间从L1数据高速缓存中加载请求的数据。在优选实施例中，当指定的时间在RTOQ中可用时，确认被发送到处理单元。

47. 发明授权

US06425090B1 Method for just-in-time delivery of load data utilizing alternating time intervals 失效
标题翻译：使用交替时间间隔即时传送负载数据的方法
公开(公告)号：US06425090B1
公开(公告)日：2002-07-23
申请号：US09338946
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F104
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3838 , G06F9/384
摘要： A method for converting a distance of dependency (DoD) value to a cycle of dependency (CoD) value is disclosed. The method comprises the steps of (i) simulating a dependency system timer (DST) on a data processing system, with the DST having a present time measured in cycles and a period, (ii) adding a DoD value of N bits to the present time to yield a resulting time of the least significant N bits of said adding step, and (iii) creating the CoD value by appending a carry over of the adding step to the resulting time, where when the carry over is not equal to zero, the carry over signals a user of the CoD value to wait until a next period before the CoD value should be applied. In one embodiment, the carry-over value is added to the value corresponding to a respective alternating period to yield an even/odd bit which determines the period.
摘要翻译：公开了将依赖距离（DoD）值转换为依赖循环（CoD）值的方法。该方法包括以下步骤：（i）在数据处理系统上模拟依赖系统定时器（DST），其中DST具有以周期和周期测量的当前时间，（ii）向目前添加N位的DoD值时间以产生所述相加步骤的最低有效N比特的结果时间，以及（iii）通过将加法步骤的进位附加到所得到的时间来创建CoD值，其中当进位不等于零时，进位信号指示CoD值的用户等待直到应用CoD值之前的下一个周期。在一个实施例中，结转值被加到对应于相应交替周期的值，以产生确定周期的偶数/奇数位。

48. 发明授权

US06418514B1 Removal of posted operations from cache operations queue 失效
标题翻译：从缓存操作队列中删除已发布的操作
公开(公告)号：US06418514B1
公开(公告)日：2002-07-09
申请号：US09024382
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.
摘要翻译：一种通过将存储器值加载到多个高速缓存块中来避免多处理器计算机系统的高速缓存一致性协议中的死锁的方法，将具有较高冲突优先级的第一相关性状态分配给仅一个高速缓存块，并且分配一个或更多的附加一致性状态对所有剩余的高速缓存块具有较低的冲突优先级。可以使用不同的系统总线代码来指示冲突请求的优先级（例如，DClaim操作）来修改存储器值。本发明还允许折叠或消除冗余DClaim操作，并且可以在具有被分组为至少两个簇的处理单元的多处理器计算机系统内以全局与局部方式应用。

49. 发明授权

US06397320B1 Method for just-in-time delivery of load data via cycle of dependency 失效
标题翻译：通过依赖循环即时传递负载数据的方法
公开(公告)号：US06397320B1
公开(公告)日：2002-05-28
申请号：US09344061
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/383 , G06F12/0811 , G06F12/0859
摘要： A method for ordering the time of issuing of a load instruction from a lower level (L2) cache controller to its L2 cache in a data processing system to enable delivery of a load data at a time it is required by its downstream dependency is disclosed. The method comprises the steps of (i) determining a cycle of dependency (CoD) of the load data, where the CoD corresponds to an exact synchronized timer (ST) time, measured in cycles, on which said data is required by said downstream dependency from the L2 cache, and (ii) issuing the load instruction to said L2 cache at said time to synchronize a providing of said data to a pipeline of a system resource with a request by its downstream dependency. In the preferred embodiment of the invention, a distance of dependency (DoD) value is first appended to the load instruction. The DoD value is then converted to a CoD value when a miss occurs at the internal (L1) cache.
摘要翻译：公开了一种在数据处理系统中排序从下一级（L2）高速缓存控制器向其二级高速缓存发出加载指令的时间的方法，以便能够在其下游依赖性所需的时间传送负载数据。该方法包括以下步骤：（i）确定负载数据的依赖循环（CoD），其中CoD对应于以周期测量的精确同步定时器（ST）时间，所述下行依赖性需要所述数据以及（ii）在所述时间向所述L2高速缓存发出加载指令，以使所述数据与系统资源的流水线通过其下游依赖关系的请求同步。在本发明的优选实施例中，首先将依赖距离（DoD）值附加到加载指令。当内部（L1）缓存发生未命中时，DoD值被转换为CoD值。

50. 发明授权

US06345340B1 Cache coherency protocol with ambiguous state for posted operations 失效
标题翻译：缓存一致性协议，具有不明确的状态，用于发布操作
公开(公告)号：US06345340B1
公开(公告)日：2002-02-05
申请号：US09024608
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.
摘要翻译：一种通过将存储器值加载到多个高速缓存块中来避免多处理器计算机系统的高速缓存一致性协议中的死锁的方法，将具有较高冲突优先级的第一相关性状态分配给仅一个高速缓存块，并且分配一个或更多的附加一致性状态对所有剩余的高速缓存块具有较低的冲突优先级。可以使用不同的系统总线代码来指示冲突请求的优先级（例如，DClaim操作）来修改存储器值。本发明还允许折叠或消除冗余DClaim操作，并且可以在具有被分组为至少两个簇的处理单元的多处理器计算机系统内以全局与局部方式应用。

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