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41. 发明申请

US20110016250A1 SYSTEM AND METHOD UTILIZING DISTRIBUTED BYTE-WISE BUFFERS ON A MEMORY MODULE 有权
标题翻译：在存储器模块中使用分布式BY-WISE缓冲器的系统和方法
公开(公告)号：US20110016250A1
公开(公告)日：2011-01-20
申请号：US12761179
申请日：2010-04-15
申请人： Hyun Lee , Jayesh R. Bhakta
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F13/28 , G06F12/00 , G06F13/40
CPC分类号： G06F12/00 , G11C5/025 , G11C5/04 , G11C5/066 , G11C8/12
摘要： A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.
摘要翻译：提供了利用一个或多个存储器模块的存储器系统和方法。存储器模块包括多个存储器件和被配置为从系统存储器控制器接收控制信息并产生模块控制信号的控制器。存储器模块还包括多个电路，例如逐字节缓冲器，其配置为将多个存储器设备与系统存储器控制器选择性地隔离。响应于模块控制信号，这些电路可操作地将写数据从系统存储器控制器驱动到多个存储器装置，并将来自多个存储器件的读取数据合并到系统存储器控制器。电路分布在彼此分开的相应位置。

42. 发明授权

US07839645B2 Module having at least two surfaces and at least one thermally conductive layer therebetween 有权
标题翻译：模块具有至少两个表面和其间的至少一个导热层
公开(公告)号：US07839645B2
公开(公告)日：2010-11-23
申请号：US12606136
申请日：2009-10-26
申请人： Robert S. Pauley , Jayesh R. Bhakta , William M. Gervasi , Chi She Chen , Jose Delvalle
发明人： Robert S. Pauley , Jayesh R. Bhakta , William M. Gervasi , Chi She Chen , Jose Delvalle
IPC分类号： H05K7/20
CPC分类号： H05K1/0203 , H05K1/144 , H05K2201/10189 , H05K2201/1056 , H05K2201/2018 , Y10T29/49117 , Y10T29/49124 , Y10T29/4913
摘要： A module is electrically connectable to a computer system. The module includes a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first surface and a first plurality of circuits coupled to the first surface. The first plurality of circuits is in electrical communication with the electrical contacts. The module further includes a second surface and a second plurality of circuits coupled to the second surface. The second plurality of circuits is in electrical communication with the electrical contacts. The second surface faces the first surface. The module further includes at least one thermally conductive layer positioned between the first surface and the second surface. The at least one thermally conductive layer is in thermal communication with the first plurality of circuits, the second plurality of circuits, and a first set of the plurality of electrical contacts.
摘要翻译：模块可电连接到计算机系统。模块包括可电连接到计算机系统的多个电触点。模块还包括耦合到第一表面的第一表面和第一多个电路。第一组多个电路与电触点电连通。模块还包括耦合到第二表面的第二表面和第二多个电路。第二组电路与电触点电连通。第二表面面向第一表面。模块还包括位于第一表面和第二表面之间的至少一个导热层。所述至少一个导热层与所述第一多个电路，所述第二多个电路和所述多个电触头的第一组热连通。

43. 发明授权

US07811097B1 Circuit with flexible portion 有权
标题翻译：具有柔性部分的电路
公开(公告)号：US07811097B1
公开(公告)日：2010-10-12
申请号：US12237162
申请日：2008-09-24
申请人： Jayesh R. Bhakta , Enchao Yu , Chi She Chen , Richard E. Flaig
发明人： Jayesh R. Bhakta , Enchao Yu , Chi She Chen , Richard E. Flaig
IPC分类号： H01R12/00
CPC分类号： H05K1/147 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H05K1/0203 , H05K1/141 , H05K3/4691 , H05K2201/10159 , H05K2201/1056 , H05K2203/1572 , H01L2224/0401
摘要： A circuit includes a first plurality of contacts configured to be in electrical communication with a plurality of electronic devices. The circuit card further includes a flexible portion including a dielectric layer, a second plurality of contacts, and a plurality of electrical conduits extending across a region of the flexible portion and in electrical communication with one or more contacts of the first plurality of contacts and with the second plurality of contacts. The flexible portion further includes an electrically conductive layer extending across the region of the flexible portion. The electrically conductive layer is superposed with the plurality of electrical conduits with the dielectric layer therebetween. The electrically conductive layer does not overlay one or more portions of the dielectric layer in the region of the flexible portion.
摘要翻译：电路包括构造成与多个电子设备电连通的第一多个触点。电路卡还包括柔性部分，该柔性部分包括电介质层，第二多个触点以及跨越柔性部分的区域延伸并且与第一多个触点的一个或多个触点电连通并且与第二个多个联系人。柔性部分还包括延伸穿过柔性部分的区域的导电层。导电层与多个电导管重叠，其间具有介电层。在柔性部分的区域中，导电层不覆盖电介质层的一个或多个部分。

44. 发明授权

US06751113B2 Arrangement of integrated circuits in a memory module 有权
公开(公告)号：US06751113B2
公开(公告)日：2004-06-15
申请号：US10094512
申请日：2002-03-07
申请人： Jayesh R. Bhakta , Robert S. Pauley, Jr.
发明人： Jayesh R. Bhakta , Robert S. Pauley, Jr.
IPC分类号： G11C506
CPC分类号： H05K1/181 , H05K1/0266 , H05K2201/09409 , H05K2201/09709 , H05K2201/10689 , Y02P70/611
摘要： Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

45. 发明授权

US08516185B2 System and method utilizing distributed byte-wise buffers on a memory module 有权
标题翻译：在存储器模块上使用分布式逐字节缓冲器的系统和方法
公开(公告)号：US08516185B2
公开(公告)日：2013-08-20
申请号：US12761179
申请日：2010-04-15
申请人： Hyun Lee , Jayesh R. Bhakta
发明人： Hyun Lee , Jayesh R. Bhakta
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G11C5/025 , G11C5/04 , G11C5/066 , G11C8/12
摘要： A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.
摘要翻译：提供了利用一个或多个存储器模块的存储器系统和方法。存储器模块包括多个存储器件和被配置为从系统存储器控制器接收控制信息并产生模块控制信号的控制器。存储器模块还包括多个电路，例如逐字节缓冲器，其配置为将多个存储器设备与系统存储器控制器选择性地隔离。响应于模块控制信号，这些电路可操作地将写数据从系统存储器控制器驱动到多个存储器装置，并将来自多个存储器件的读取数据合并到系统存储器控制器。电路分布在彼此分开的相应位置。

46. 发明申请

US20120239874A1 METHOD AND SYSTEM FOR RESOLVING INTEROPERABILITY OF MULTIPLE TYPES OF DUAL IN-LINE MEMORY MODULES 审中-公开
标题翻译：用于解决多种类型的在线存储器模块的互操作性的方法和系统
公开(公告)号：US20120239874A1
公开(公告)日：2012-09-20
申请号：US13411344
申请日：2012-03-02
申请人： Hyun Lee , Jayesh R. Bhakta , Paresh Sheth
发明人： Hyun Lee , Jayesh R. Bhakta , Paresh Sheth
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1673
摘要： Systems and methods are described for resolving certain interoperability issues among multiple types of memory modules in the same memory subsystem. The system provides a single data load DIMM for constructing a high density and high speed memory subsystem that supports the standard JEDEC RDIMM interface while presenting a single load to the memory controller. At least one memory module includes one or more DRAM, a bi-directional data buffer and an interface bridge with a conflict resolution block. The interface bridge translates the CAS latency (CL) programming value that a memory controller sends to program the DRAMs, modifies the latency value, and is used for resolving command conflicts between the DRAMs and the memory controller to insure proper operation of the memory subsystem.
摘要翻译：描述了系统和方法，用于解决同一内存子系统中多种类型的内存模块之间的某些互操作性问题。该系统提供单个数据加载DIMM，用于构建高密度和高速存储器子系统，支持标准JEDEC RDIMM接口，同时向存储器控制器提供单个负载。至少一个存储器模块包括一个或多个DRAM，双向数据缓冲器和具有冲突解决块的接口桥。接口桥转换存储器控制器向DRAM编程的CAS延迟（CL）编程值，修改延迟值，并用于解决DRAM和存储器控制器之间的命令冲突，以确保存储器子系统的正确操作。

47. 发明授权

US06930900B2 Arrangement of integrated circuits in a memory module 有权
公开(公告)号：US06930900B2
公开(公告)日：2005-08-16
申请号：US10765420
申请日：2004-01-27
申请人： Jayesh R. Bhakta , Robert S. Pauley, Jr.
发明人： Jayesh R. Bhakta , Robert S. Pauley, Jr.
IPC分类号： G11C5/00 , H05K1/02 , H05K1/18 , G11C5/06 , G06F12/00 , G06F13/00 , G11C5/02 , G11C19/00
CPC分类号： H05K1/181 , H05K1/0266 , H05K2201/09409 , H05K2201/09709 , H05K2201/10689 , Y02P70/611
摘要： Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

48. 发明授权

US06222739B1 High-density computer module with stacked parallel-plane packaging 有权
标题翻译：具有堆叠平行平面封装的高密度计算机模块
公开(公告)号：US06222739B1
公开(公告)日：2001-04-24
申请号：US09228867
申请日：1999-01-12
申请人： Jayesh R. Bhakta , Kavous Vakilian
发明人： Jayesh R. Bhakta , Kavous Vakilian
IPC分类号： H05K111
CPC分类号： G06F1/186 , G06F1/184 , G06F1/185 , H01L25/105 , H01L25/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/107 , H01L2924/0002 , H01R12/721 , H05K1/144 , H05K7/1431 , H01L2924/00
摘要： A module for insertion into an expansion slot of a computer includes a primary board and a pair of auxiliary boards. The auxiliary boards are mounted in a spaced relationship on respective sides of the primary board to define air paths between the boards. The air paths allow air to circulate between the boards. The auxiliary boards each have a trace for electrically connecting the board to the primary board, and the primary board has a trace for connecting chips mounted thereon to an interface with the expansion slot. The traces of the auxiliary boards are substantially the same length. The trace of the primary boards is only slightly longer than the traces of the auxiliary boards.
摘要翻译：用于插入到计算机的扩展槽中的模块包括主板和一对辅助板。辅助板在主板的相应侧面上以间隔的关系安装，以限定板之间的空气路径。空气路径允许空气在板之间循环。辅助板各自具有用于将板电连接到主板的迹线，并且主板具有用于将安装在其上的芯片连接到与扩展槽的接口的迹线。辅助板的迹线基本上相同的长度。主板的轨迹只比辅助板的轨迹略长。

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