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41. 发明申请

US20080320421A1 FEATURE EXTRACTION THAT SUPPORTS PROGRESSIVELY REFINED SEARCH AND CLASSIFICATION OF PATTERNS IN A SEMICONDUCTOR LAYOUT 审中-公开
标题翻译：特征提取，支持进行精细化的搜索和分类在半导体布局中的图案
公开(公告)号：US20080320421A1
公开(公告)日：2008-12-25
申请号：US11765473
申请日：2007-06-20
申请人： David L. Demaris , Rouwaida N. Kanj , Daniel N. Maynard , Michael D. Monkowski
发明人： David L. Demaris , Rouwaida N. Kanj , Daniel N. Maynard , Michael D. Monkowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A system, method and program product for searching and classifying patterns in a VLSI design layout. A method is provided that includes generating a target vector using a two dimensional (2D) low discrepancy sequence; identifying layout regions in a design layout; generating a feature vector for a layout region; comparing a subset of sequence values in the target vector with sequence values in the feature vector as an initial filter, wherein the system for comparing determines that the layout region does not contain a match if a comparison of the subset of sequence values in the target vector with sequence values in the feature vector falls below a threshold; and outputting search results.
摘要翻译：一种用于在VLSI设计布局中搜索和分类模式的系统，方法和程序产品。提供了一种方法，其包括使用二维（2D）低差异序列生成目标矢量; 识别设计布局中的布局区域; 生成布局区域的特征向量; 将目标矢量中的序列值的子集与特征向量中的序列值作为初始过滤器进行比较，其中用于比较的系统确定如果比较目标向量中的序列值子集，布局区域不包含匹配特征向量中的序列值低于阈值; 并输出搜索结果。

42. 发明授权

US06738954B1 Method for prediction random defect yields of integrated circuits with accuracy and computation time controls 有权
标题翻译：用于精确计算时间控制的集成电路预测随机缺陷产量的方法
公开(公告)号：US06738954B1
公开(公告)日：2004-05-18
申请号：US09636478
申请日：2000-08-10
申请人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
发明人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
IPC分类号： G06F1750
CPC分类号： H01L22/20 , G01R31/31705
摘要： A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.
摘要翻译：一种计算具有装置形状的集成电路的制造成品率的方法包括将集成电路分为故障机构细分（每个故障机构细分包括一个或多个故障机制，并且每个故障机制包括一个或多个缺陷机构），将故障机制细分为每个区域的分区，预处理每个分区中的设备形状，通过对每个分区的每个故障机制和每个分区的平均故障概率的数值积分计算每个故障机制的初始平均故障数故障机制（数值积分产生每个缺陷机制的缺陷尺寸列表，初始平均值的计算包括设置最大积分误差极限，每个缺陷尺寸的总体最大样本量，每个故障的可允许故障mechansim），并计算最终的平均数fau 通过迭代地减少每个故障机制的初始平均故障数量的统计误差，直到统计误差低于误差极限为止，用于集成电路。

43. 发明授权

US6021267A Aspect ratio program for optimizing semiconductor chip shape 失效
标题翻译：用于优化半导体芯片形状的宽高比程序
公开(公告)号：US6021267A
公开(公告)日：2000-02-01
申请号：US925513
申请日：1997-09-08
申请人： Jeffrey P. Bonn , Daniel N. Maynard , Sharon B. Sisler , Richard C. Whiteside
发明人： Jeffrey P. Bonn , Daniel N. Maynard , Sharon B. Sisler , Richard C. Whiteside
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70425
摘要： A cost-based algorithm determines semiconductor chip aspect ratios which minimize lithographic processing costs and determines optimum chip matrices for various types of lithographic tools.
摘要翻译：基于成本的算法确定半导体芯片纵横比，其最小化光刻处理成本并确定各种类型的光刻工具的最佳芯片矩阵。

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