专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20060277370A1 Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout 有权
公开(公告)号：US20060277370A1
公开(公告)日：2006-12-07
申请号：US11146443
申请日：2005-06-06
申请人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associated storage location does not contain valid data, and a memory block identified by the address tag is likely cached outside the first coherency domain. In response to snooping a castout operation, the first cache memory determines if the castout operation hits in the entry and, if so, updates the coherency state field from the first state to a second state indicating that the associated address tag is invalid.

42. 发明申请

US20060184748A1 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
公开(公告)号：US20060184748A1
公开(公告)日：2006-08-17
申请号：US11056740
申请日：2005-02-11
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

43. 发明申请

US20060179238A1 Store stream prefetching in a microprocessor 失效
标题翻译：在微处理器中存储流预取
公开(公告)号：US20060179238A1
公开(公告)日：2006-08-10
申请号：US11054871
申请日：2005-02-10
申请人： John Griswell , Hung Le , Francis O'Connell , William Starke , Jeffrey Stuecheli , Albert Williams
发明人： John Griswell , Hung Le , Francis O'Connell , William Starke , Jeffrey Stuecheli , Albert Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/30047 , G06F9/383 , G06F12/0811
摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.
摘要翻译：在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。预取引擎将预取队列中的条目与两个连续高速缓存块的窗口进行比较。当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

44. 发明申请

US20060179222A1 System bus structure for large L2 cache array topology with different latency domains 失效
标题翻译：具有不同延迟域的大二级缓存阵列拓扑的系统总线结构
公开(公告)号：US20060179222A1
公开(公告)日：2006-08-10
申请号：US11054925
申请日：2005-02-10
申请人： Vicente Chung , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Vicente Chung , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses. The first data bus can be one of a plurality of data busses in a first data bus set, and the second data bus can be one of a plurality of data busses in a second data bus set. Two address busses (one for each data bus set) are used to receive successive address tags that identify which portions of the requested memory values are being received from each data bus set. For example, the requested memory values may be 32 bytes each, and the separate portions of the requested memory values are received over four successive cycles with an 8-byte portion of each value received each cycle. The cache lines are spread across different cache sectors of the cache memory, wherein the cache sectors have different output latencies, and the separate portions of a given requested memory value are loaded sequentially into the corresponding cache sectors based on their respective output latencies. Merge flow circuits responsive to the cache controller are used to receive the portions of a requested memory value and input those bytes into the cache sector.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。第一数据总线可以是第一数据总线组中的多个数据总线之一，并且第二数据总线可以是第二数据总线组中的多个数据总线中的一个。两个地址总线（每个数据总线集合一个）用于接收连续的地址标签，其识别从每个数据总线组接收到所请求的存储器值的哪些部分。例如，所请求的存储器值可以是每个32个字节，并且所请求的存储器值的分开的部分在四个连续周期中被接收，每个周期接收每个值的8字节部分。高速缓存行分布在高速缓冲存储器的不同高速缓存扇区上，其中高速缓存扇区具有不同的输出延迟，并且给定请求的存储器值的分离部分基于它们各自的输出延迟顺序地加载到相应的高速缓存扇区中。响应于高速缓存控制器的合并流回路用于接收请求的存储器值的部分并将这些字节输入高速缓存扇区。

45. 发明申请

US20060095691A1 Processor, method, and data processing system employing a variable store gather window 有权
标题翻译：处理器，方法和数据处理系统采用变量存储收集窗口
公开(公告)号：US20060095691A1
公开(公告)日：2006-05-04
申请号：US10922272
申请日：2004-08-19
申请人： Robert Bell , Hugh Shen , Jeffrey Stuecheli , Derek Williams
发明人： Robert Bell , Hugh Shen , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

46. 发明申请

US20050108605A1 Pseudo random test pattern generation using Markov chains 失效
标题翻译：使用马尔可夫链的伪随机测试模式生成
公开(公告)号：US20050108605A1
公开(公告)日：2005-05-19
申请号：US09737347
申请日：2000-12-15
申请人： Jeffrey Stuecheli
发明人： Jeffrey Stuecheli
IPC分类号： G01R31/28 , G01R31/3183 , G06F17/50
CPC分类号： G01R31/318357 , G01R31/318307 , G01R31/318385 , G06F17/5022
摘要： A driver module is provided that generates test patterns with desired tendencies. The driver module provides these test patterns to controlling code for simulation of a hardware model. The test patterns are generated by creating and connecting subgraphs in a Markov chain. The Markov model describes a plurality of states, each having a probability of going to at least one other state. Markov models may be created to determine whether to drive an interface in the hardware model and to determine the command to drive through the interface. Once the driver module creates and connects the subgraphs of the Markov models, the driver module initiates a random walk through the Markov chains and provides the commands to the controlling code.
摘要翻译：提供了一个驱动程序模块，可以生成具有所需趋势的测试模式。驱动程序模块提供这些测试模式来控制硬件模型仿真的代码。测试模式是通过在马尔可夫链中创建和连接子图来生成的。马尔可夫模型描述了多个状态，每个状态具有进入至少一个其他状态的概率。可以创建马尔可夫模型来确定是否驱动硬件模型中的接口，并确定通过接口驱动的命令。一旦驱动程序模块创建并连接马尔科夫模型的子图，驱动程序模块将通过马尔可夫链启动随机游走，并向控制代码提供命令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式