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41. 发明授权

US07148074B1 Method and apparatus for using a capacitor array to measure alignment between system components 有权
标题翻译：使用电容器阵列来测量系统部件之间的对准的方法和装置
公开(公告)号：US07148074B1
公开(公告)日：2006-12-12
申请号：US10820662
申请日：2004-04-07
申请人： Robert J. Drost , Ronald Ho , Robert J. Proebsting
发明人： Robert J. Drost , Ronald Ho , Robert J. Proebsting
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L25/50 , H01L25/0657 , H01L2225/06513 , H01L2225/06531 , H01L2225/06534 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a system that measures alignment between a first semiconductor die and a second semiconductor die. The system operates by applying a pattern of voltage signals to a two-dimensional array of conductive transmitter elements that form a transmitter array on the first semiconductor die. This transmitter array is positioned over a corresponding two-dimensional array of conductive receiver elements that form a receiver array on the second semiconductor die, whereby a voltage signal applied to a transmitter element induces a voltage signal in one or more receiver elements. The system amplifies voltage signals induced in receiver elements in the receiver array, and subsequently analyzes the amplified signals to determine an alignment between the first semiconductor die and the second semiconductor die.
摘要翻译：本发明的一个实施例提供一种测量第一半导体管芯和第二半导体管芯之间的对准的系统。该系统通过将电压信号的图案应用于在第一半导体管芯上形成发射器阵列的导电发射器元件的二维阵列来进行操作。该发射器阵列位于形成第二半导体管芯上的接收器阵列的导电接收器元件的对应的二维阵列上，由此施加到发射器元件的电压信号在一个或多个接收器元件中感应电压信号。该系统放大在接收器阵列中的接收器元件中感应的电压信号，随后分析放大的信号以确定第一半导体管芯和第二半导体管芯之间的对准。

42. 发明授权

US07106079B2 Using an interposer to facilate capacitive communication between face-to-face chips 有权
标题翻译：使用插入器来提升面对面芯片之间的电容性通信
公开(公告)号：US07106079B2
公开(公告)日：2006-09-12
申请号：US10973114
申请日：2004-10-22
申请人： Robert J. Drost , Ronald Ho , Robert J. Proebsting
发明人： Robert J. Drost , Ronald Ho , Robert J. Proebsting
IPC分类号： G01R31/00
CPC分类号： H01L23/48 , H01L23/49827 , H01L23/49833 , H01L23/552 , H01L24/72 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/30105
摘要： A system that improves communications between capacitively coupled integrated circuit chips. The system operates by situating an interposer over capacitive communication pads on a first integrated circuit chip, wherein the interposer is made up of material that is anisotropic with respect to transmitting capacitive signals. A second integrated circuit chip is situated so that communication pads on the second integrated circuit chip are aligned to capacitively couple signals between the integrated circuit chips through the interposer. The increased dielectric permittivity caused by the interposer can improve capacitive coupling between opposing communication pads on the integrated circuit chips. The interposer can also reduce cross talk between communication pads on the first integrated circuit chip and pads adjacent to the opposing communication pads on the second integrated circuit chip.
摘要翻译：一种改善电容耦合集成电路芯片之间通信的系统。该系统通过在第一集成电路芯片上的电容性通信焊盘上设置插入器来工作，其中插入器由相对于传输电容性信号是各向异性的材料构成。第二集成电路芯片被定位成使得第二集成电路芯片上的通信焊盘对齐以通过插入器电容耦合在集成电路芯片之间的信号。由插入器引起的增加的介电常数可以改善集成电路芯片上相对的通信焊盘之间的电容耦合。插入器还可以减少第一集成电路芯片上的通信焊盘与第二集成电路芯片上相对的通信焊盘相邻的焊盘之间的串扰。

43. 发明授权

US07085178B1 Low-power memory write circuits 有权
标题翻译：低功耗存储器写入电路
公开(公告)号：US07085178B1
公开(公告)日：2006-08-01
申请号：US11045940
申请日：2005-01-27
申请人： Robert J. Proebsting , Ronald Ho , Robert J. Drost
发明人： Robert J. Proebsting , Ronald Ho , Robert J. Drost
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/1096 , G11C2207/2227
摘要： One embodiment of the present invention provides a system that writes to a cell in a memory using a low-voltage-swing signal across a pair of global bit-lines. During operation, the system receives a low-voltage-swing signal across a pair of global bit-lines, which is too low to reliably write the memory cell. Next, the system converts the low-voltage-swing signal to a high-voltage-swing signal, which is adequate to reliably write the memory cell. The system then writes to the memory cell by applying the high-voltage-swing signal across a pair of local bit-lines that are coupled to the memory cell. The use of low-voltage-swing signals on the global bit-lines reduces overall power consumption. Furthermore, in one embodiment of the present invention, the voltage conversion is achieved using a pair of cross-coupled NMOS transistors whose sources are directly or indirectly coupled with the global bit-lines, and whose drains are directly or indirectly coupled with the local bit-lines.
摘要翻译：本发明的一个实施例提供一种使用跨越一对全局位线的低电压摆幅信号向存储器中的单元写入的系统。在运行期间，系统通过一对全局位线接收低电压摆幅信号，该位线太低而无法可靠地写存储单元。接下来，系统将低电压摆幅信号转换成高电压摆幅信号，这足以可靠地写入存储单元。然后，系统通过将耦合到存储器单元的一对本地位线施加高电压摆幅信号来写入存储器单元。在全局位线上使用低电压摆幅信号可以降低总体功耗。此外，在本发明的一个实施例中，使用一对交叉耦合的NMOS晶体管实现电压转换，其中源极与全局位线直接或间接耦合，并且其漏极与本地位直接或间接耦合线。

44. 发明授权

US07046017B1 Full-wave rectifier for capacitance measurements 有权
标题翻译：全波整流电容测量
公开(公告)号：US07046017B1
公开(公告)日：2006-05-16
申请号：US11216754
申请日：2005-08-30
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01R27/26 , G01N27/22
CPC分类号： G01R27/2605
摘要： One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种用于测量电容的电子电路和方法。信号发生机构在电容的一个端子上产生具有预定频率和预定义的低和高电压电平的信号。电容的另一个端子耦合到开关机构。开关机构被设置为将电容的另一个端子耦合到每个信号周期的一部分的第一放大器或第二放大器，由此对在电容中的两个端子之间流动的瞬态电流进行全波整流。第一放大器和第二放大器的输出耦合到用于测量电流的电流测量机构。电容由测量电流确定。提供了该实施例的几个变型。

45. 发明授权

US06987394B1 Full-wave rectifier for capacitance measurements 有权
公开(公告)号：US06987394B1
公开(公告)日：2006-01-17
申请号：US10879608
申请日：2004-06-28
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01R27/26
CPC分类号： G01R27/2605
摘要： One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.

46. 发明授权

US08472206B2 Method for reducing power consumption by using capacitive coupling to perform majority detection 有权
标题翻译：通过使用电容耦合来执行多数检测来降低功耗的方法
公开(公告)号：US08472206B2
公开(公告)日：2013-06-25
申请号：US13235152
申请日：2011-09-16
申请人： Ronald Ho , Robert J. Drost , Robert Hopkins
发明人： Ronald Ho , Robert J. Drost , Robert Hopkins
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： G06F1/189
摘要： One embodiment of the present invention provides a method that reduces power consumption by using capacitive coupling to perform a majority detection operation. The method involves driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. In addition, method involves feeding a signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The method further involves using the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by a computer system.
摘要翻译：本发明的一个实施例提供一种通过使用电容耦合来执行多数检测操作来降低功耗的方法。该方法涉及将多个信号驱动到多个从动导线上。然后，这些信号从每个从动导线通过相应的耦合电容器馈送到单个多数检测线。此外，方法包括将多个检测线上的信号和偏置电压馈送到差分接收器。如果多数检测线上的信号相对于偏置电压切换，差分接收器的输出将切换。该方法还包括使用差分接收器的输出来优化来自多条驱动线的信号，以便在长信号路径上传输。优化信号传输减少了计算机系统消耗的功耗。

47. 发明申请

US20110302465A1 MISALIGNMENT COMPENSATION FOR PROXIMITY COMMUNICATION 有权
标题翻译：缺席通信补偿
公开(公告)号：US20110302465A1
公开(公告)日：2011-12-08
申请号：US13212900
申请日：2011-08-18
申请人： Ronald Ho , Ashok V. Krishnamoorthy , John E. Cunningham , Robert J. Drost
发明人： Ronald Ho , Ashok V. Krishnamoorthy , John E. Cunningham , Robert J. Drost
IPC分类号： G06F11/07
CPC分类号： H04B5/0075 , H01L25/065 , H01L2924/0002 , H04B17/318 , H04L1/0009 , Y10T29/49133 , H01L2924/00
摘要： In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels.
摘要翻译：在接近通信系统中，一个芯片上的发射元件与与第一芯片并置的第二芯片上的接收元件对齐。然而，如果元件是静态的或动态的，则芯片之间的耦合会降低。可以通过可控地降低系统的性能来补偿未对准。例如，可以增加发射信号强度。可以增加用于偏置每个位的位周期或时间段，从而降低带宽。诸如电容器的多个耦合元件可以组合在一起，从而减少通道数量。可以通过减少每个符号的比特数来增加诸如图像的符号的粒度。诸如电容器的多个耦合元件可以组合在一起，从而减少通道数量。

48. 发明申请

US20100244288A1 METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR CHIPS USING VARYING AREAS OF PRECISION 审中-公开
标题翻译：使用精度变化区域制作半导体器件的方法和装置
公开(公告)号：US20100244288A1
公开(公告)日：2010-09-30
申请号：US12813808
申请日：2010-06-11
申请人： David C. Douglas , Ronald Ho , Robert J. Drost
发明人： David C. Douglas , Ronald Ho , Robert J. Drost
IPC分类号： H01L23/544 , G03B27/52
CPC分类号： G03F7/70433
摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.
摘要翻译：制造半导体芯片的系统。系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。

49. 发明授权

US07786427B2 Proximity optical memory module having an electrical-to-optical and optical-to-electrical converter 有权
标题翻译：接近光学存储器模块，其具有电 - 光和光 - 电转换器
公开(公告)号：US07786427B2
公开(公告)日：2010-08-31
申请号：US12115989
申请日：2008-05-06
申请人： Craig S. Forrest , Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Craig S. Forrest , Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01J1/04
CPC分类号： G11C5/04 , G11C5/143 , G11C7/1051 , G11C7/1054 , G11C7/1078 , G11C7/1081 , H01L23/48 , H01L23/642 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/167 , H01L2225/06562 , H01L2924/01067 , H01L2924/14 , H01L2924/19041
摘要： A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.
摘要翻译：存储器模块由多个存储器芯片和固定在基板上的光学接口芯片形成。芯片通过邻近通信（PxC）相互连接，其中每个芯片包括发射和接收元件，例如当芯片彼此面对放置在一起时形成电容耦合链路的电焊盘。 PxC链路可以直接在芯片之间或通过中间无源桥芯片。接口芯片耦合到外部光通道并且包括用于与存储器芯片通信的光学和电信号之间的转换器，控制电路，缓冲器和PxC元件。存储器阵列可以是形成冗余PxC网络的接口芯片周围的线性或二维阵列，可选地具有冗余PxC连接。多个矩形存储器芯片可以将它们的窄边呈现给接口芯片以最大化带宽。

50. 发明授权

US07715420B1 Method and apparatus for refreshing receiver circuits using extra communication bits 有权
标题翻译：使用额外的通信位刷新接收机电路的方法和装置
公开(公告)号：US07715420B1
公开(公告)日：2010-05-11
申请号：US11651222
申请日：2007-01-05
申请人： Robert J. Drost , Ronald Ho
发明人： Robert J. Drost , Ronald Ho
IPC分类号： H04L12/28
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： One embodiment of the present invention provides a system that facilitates biasing receiver circuits within an integrated circuit. During operation, the system provides n receiver circuits within the integrated circuit to be biased. Next, the system provides n+m communication channels between n drivers and n receivers, wherein m is a number of additional communication channels, and wherein m>0. Then, the system couples the n+m communication channels to the n drivers, wherein each driver is selectively coupled to m+1 communication channels. The system also couples the n+m communication channels to the n receivers, wherein each receiver is selectively coupled to m+1 communication channels. In this way, at any given time n of the communication channels are active and m of the communication channels are inactive. Finally, the system refreshes inactive m communication channels' biases while the m inactive communication channels are not communicating signals.
摘要翻译：本发明的一个实施例提供了一种便于在集成电路内偏置接收器电路的系统。在运行期间，系统提供集成电路内的n个接收器电路以进行偏置。接下来，该系统在n个驱动器和n个接收器之间提供n + m个通信信道，其中m是多个附加通信信道，并且其中m> 0。然后，系统将n + m通信信道耦合到n个驱动器，其中每个驱动器选择性地耦合到m + 1个通信信道。该系统还将n + m个通信信道耦合到n个接收机，其中每个接收机选择性地耦合到m + 1个通信信道。以这种方式，在任何给定的时间，n个通信信道是有效的，并且通信信道的m是无效的。最后，当m个无效通信信道不通信信号时，系统刷新无效的通信信道偏移。

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