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41. 发明授权

US09640633B1 Self aligned gate shape preventing void formation 有权
公开(公告)号：US09640633B1
公开(公告)日：2017-05-02
申请号：US14974589
申请日：2015-12-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc. , STMicroelectronics, Inc.
发明人： Andrew M. Greene , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/66 , H01L29/78 , H01L21/02 , H01L21/306
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66515 , H01L29/66795 , H01L29/785
摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

42. 发明申请

US20160284607A1 DUAL CHANNEL FINFET WITH RELAXED PFET REGION 有权
标题翻译：具有松弛PFET区域的双通道FINFET
公开(公告)号：US20160284607A1
公开(公告)日：2016-09-29
申请号：US14670800
申请日：2015-03-27
申请人： International Business Machines Corporation , GLOBALFOUNDRIES, Inc. , STMICROELECTRONICS, INC.
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/84 , H01L29/78 , H01L27/12
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7849
摘要： Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.
摘要翻译：制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分可流动的氧化物。

43. 发明申请

US20160284602A1 MACRO TO MONITOR N-P BUMP 有权
标题翻译：宏观监控N-P BUMP
公开(公告)号：US20160284602A1
公开(公告)日：2016-09-29
申请号：US14669055
申请日：2015-03-26
申请人： International Business Machines Corporation , Globalfoundries, Inc. , STMicroelectronics, Inc.
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L21/306 , H01L21/308 , H01L21/66 , H01L21/768
CPC分类号： H01L21/823871 , H01L21/30625 , H01L21/3085 , H01L21/82385 , H01L22/12 , H01L22/30
摘要： A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.
摘要翻译：技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。宏是根据制造工艺制造的。该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。进行化学机械抛光以除去宏观上的n-p凸块。先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。

44. 发明申请

US20160181381A1 TRENCH EPITAXIAL GROWTH FOR A FINFET DEVICE HAVING REDUCED CAPACITANCE 有权
标题翻译：用于具有降低电容的FINFET器件的外延生长
公开(公告)号：US20160181381A1
公开(公告)日：2016-06-23
申请号：US14577431
申请日：2014-12-19
申请人： STMicroelectronics, Inc. , International Business Machines Corporation , GlobalFoundries Inc
发明人： Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/417 , H01L29/66 , H01L29/06 , H01L29/78
CPC分类号： H01L29/41783 , H01L29/0653 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.
摘要翻译： FinFET器件包括半导体鳍片，在鳍片的沟道上延伸的栅极电极和在栅电极的每一侧上的侧壁间隔物。电介质材料位于所述散热片的底部的每一侧上，其中在散热片的每侧的氧化物材料覆盖在电介质材料上。在通道区域的每一侧的翅片上形成的凹陷区域由氧化物材料界定。凸起的源极区域填充凹陷区域并且在栅电极的第一侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。凸起的漏极区域填充凹陷区域并且在栅电极的第二侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。

45. 发明申请

US20160163850A1 LDMOS FINFET DEVICE AND METHOD OF MANUFACTURE USING A TRENCH CONFINED EPITAXIAL GROWTH PROCESS 有权
标题翻译： LDMOS FINFET器件和使用TRENCH CONFINED外延生长工艺制造的方法
公开(公告)号：US20160163850A1
公开(公告)日：2016-06-09
申请号：US14560255
申请日：2014-12-04
申请人： STMicroelectronics, Inc. , International Business Machines Corporation , GlobalFoundries Inc
发明人： Qing Liu , Ruilong Xie , Chun-Chen Yeh , Xiuyu Cai
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L27/092 , H01L29/08
CPC分类号： H01L29/785 , H01L21/823418 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/0886 , H01L29/41758 , H01L29/41791 , H01L29/66545 , H01L29/66659 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7835 , H01L29/7848
摘要： A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.
摘要翻译： FinFET晶体管包括具有在沟道区域上延伸的晶体管栅电极的半导体材料的鳍。从晶体管栅电极的两侧的鳍延伸的第一外延生长材料的引出源区和漏区。源极和漏极接触开口延伸穿过预金属化电介质材料以到达升高的源极和漏极区域。第二外延生长材料的源极和漏极接触区域在源极和漏极接触开口的底部处从第一外延生长材料延伸。金属材料填充源极和漏极接触开口，以分别与源极和漏极接触区域形成源极和漏极接触。漏极接触区域可以从晶体管栅电极偏移足以在第一外延生长材料的升高的源极区域内提供横向扩散的金属氧化物半导体（LDMOS）配置的偏移距离。

46. 发明授权

US10396000B2 Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions 有权
公开(公告)号：US10396000B2
公开(公告)日：2019-08-27
申请号：US14789476
申请日：2015-07-01
申请人： International Business Machines Corporation , Globalfoundries, Inc.
发明人： Tenko Yamashita , Chun-Chen Yeh , Hui Zang
IPC分类号： H01L21/66 , H01L29/66 , H01L21/8234 , H01L27/088
摘要： Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

47. 发明申请

US20160372380A1 DUAL LINER SILICIDE 有权
标题翻译：双层硅胶
公开(公告)号：US20160372380A1
公开(公告)日：2016-12-22
申请号：US14740987
申请日：2015-06-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/66
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76897 , H01L21/823814 , H01L21/823864 , H01L23/5226 , H01L27/092 , H01L29/0847 , H01L29/41725 , H01L29/456 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
摘要翻译：制造双硅化物器件的方法包括：生长用于N型器件的源极和漏极（S / D）区域，在栅极结构上形成保护层，并且在N型器件的S / D区域上生长S / D区域用于P型设备。第一电介质层被共形沉积，部分被去除以暴露S / D区域。用于P型器件的暴露的S / D区域被硅化以形成衬垫。第二电介质层被共形沉积。在第二电介质层上形成电介质填充物。接触孔通过第二介电层打开，露出P型器件的衬垫，露出N型器件的保护层。通过打开保护层来暴露N型器件的S / D区域。暴露的与栅极结构相邻的S / D区域被硅化以形成用于N型器件的衬垫。触点形成。

48. 发明申请

US20150140698A1 TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS 审中-公开
公开(公告)号：US20150140698A1
公开(公告)日：2015-05-21
申请号：US14607161
申请日：2015-01-28
申请人： International Business Machines Corporation , GlobalFoundries, Inc.
发明人： Tenko Yamashita , Chun-Chen Yeh , Jin Cho , Hui Zang
IPC分类号： H01L21/66 , H01L21/8234
CPC分类号： H01L22/14 , G03F7/70466 , H01L21/823431 , H01L22/10 , H01L22/12 , H01L22/34
摘要： A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

49. 发明申请

US20150140697A1 TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS 有权
标题翻译：使用多模式图像处理的测试方法
公开(公告)号：US20150140697A1
公开(公告)日：2015-05-21
申请号：US14607160
申请日：2015-01-28
申请人： International Business Machines Corporation , GlobalFoundries, Inc.
发明人： Tenko Yamashita , Chun-Chen Yeh , Jin Cho , Hui Zang
IPC分类号： H01L21/66 , H01L21/8234
CPC分类号： H01L22/14 , G03F7/70466 , H01L21/823431 , H01L22/10 , H01L22/12 , H01L22/34
摘要： A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
摘要翻译：提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

50. 发明授权

US10395995B2 Dual liner silicide 有权
公开(公告)号：US10395995B2
公开(公告)日：2019-08-27
申请号：US15956082
申请日：2018-04-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/417 , H01L29/08 , H01L29/45 , H01L23/522 , H01L21/768 , H01L21/285
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

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