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41. 发明申请

US20150035073A1 ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES 有权
标题翻译：提高可靠性和更换门阵列和FinFET结构的可移动性
公开(公告)号：US20150035073A1
公开(公告)日：2015-02-05
申请号：US13959375
申请日：2013-08-05
申请人： GLOBALFOUNDRIES Inc. , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takashi Ando , Eduard A. Cartier , Kisik Choi , Wing L. Lai , Vijay Narayanan , Ravikumar Ramachandran
IPC分类号： H01L21/28 , H01L27/092
CPC分类号： H01L21/28229 , H01L21/28185 , H01L21/823821 , H01L21/823842 , H01L27/092 , H01L27/0924 , H01L29/0649 , H01L29/42364 , H01L29/495 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7851
摘要： A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.
摘要翻译：一种用于半导体制造的方法包括在栅腔中的介电层上形成扩散阻挡层和含金属层中的至少一个。执行第一退火以将元件从扩散阻挡层和含金属层中的至少一个扩散到电介质层中。去除含金属层和扩散阻挡层。执行第二次退火以调节介电层中的元件的扩散以提供栅极电介质区域。

42. 发明授权

US08932923B2 Semiconductor gate structure for threshold voltage modulation and method of making same 有权
标题翻译：用于阈值电压调制的半导体栅极结构及其制造方法
公开(公告)号：US08932923B2
公开(公告)日：2015-01-13
申请号：US13770493
申请日：2013-02-19
申请人： Globalfoundries, Inc.
发明人： Hoon Kim , Kisik Choi
IPC分类号： H01L21/8238 , H01L29/40 , H01L29/49
CPC分类号： H01L29/401 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.
摘要翻译：具有NFET和PFET的半导体器件的栅极结构包括在NFET和PFET的栅极上方的基于铪的电介质的下层和镧系元素电介质的上层。将电介质退火以将其混合在NFET上方，导致降低的功函数和相应的阈值电压降低。在NFET栅极上方的混合电介质上的退火的较厚的氮化钛盖也降低了功函数和阈值电压。在PFET栅极上的TiN盖和铪基电介质之上，是未经退火的另一层氮化钛。钨的导电层覆盖该结构。

43. 发明申请

US20140367790A1 METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES 有权
标题翻译：基于CMOS的集成电路产品和结果设备的门结构形成方法
公开(公告)号：US20140367790A1
公开(公告)日：2014-12-18
申请号：US13919676
申请日：2013-06-17
申请人： GLOBALFOUNDRIES Inc.
发明人： Kisik Choi , Ruilong Xie
IPC分类号： H01L21/8234 , H01L27/092 , H01L21/28
CPC分类号： H01L21/823443 , H01L21/28008 , H01L21/823835 , H01L21/823842 , H01L27/092 , H01L29/66545
摘要： One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.
摘要翻译：本文公开的一种说明性方法包括通过从相同的材料形成栅极绝缘层和用于器件的第一金属层并且仅在第一金属层上选择性地形成金属硅化物材料层来形成用于NMOS晶体管和PMOS晶体管的替代栅极结构对于NMOS器件，但不在PMOS器件上。本文公开的新颖的集成电路产品的一个示例包括NMOS器件和PMOS器件，其中栅极绝缘层和器件的栅极结构的第一金属层由相同的材料制成，NMOS器件的栅极结构包括位于所述NMOS器件的所述第一金属层上的金属硅化物材料，以及位于所述NMOS器件的所述金属硅化物材料上以及所述PMOS器件的所述第一金属层上的第二金属层。

44. 发明申请

US20140367788A1 METHODS OF FORMING GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS AND THE RESULTING DEVICES 有权
标题翻译：基于CMOS的集成电路产品和结果设备的门结构形成方法
公开(公告)号：US20140367788A1
公开(公告)日：2014-12-18
申请号：US13918569
申请日：2013-06-14
申请人： GLOBALFOUNDRIES INC.
发明人： Ruilong Xie , Kisik Choi
IPC分类号： H01L21/8234 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L29/42356 , H01L29/4975
摘要： One illustrative method disclosed herein includes forming gate insulation layers and a first metal layer for NMOS and PMOS devices from the same material, selectively forming a first metal layer only for the PMOS device, and forming different shaped metal silicide regions within the NMOS and PMOS gate cavities. A novel integrated circuit product disclosed herein includes an NMOS transistor with an NMOS gate insulation layer, an NMOS metal silicide having a generally rectangular cross-sectional configuration and an NMOS metal layer positioned on the NMOS metal silicide region. The product also includes a PMOS transistor with the same gate insulation material, a first PMOS metal and a PMOS metal silicide region, wherein the NMOS and PMOS metal silicide regions are comprised of the same metal silicide.
摘要翻译：本文公开的一种说明性方法包括从相同材料形成用于NMOS和PMOS器件的栅极绝缘层和第一金属层，仅选择性地形成用于PMOS器件的第一金属层，以及在NMOS和PMOS栅极内形成不同形状的金属硅化物区域空腔本文公开的新型集成电路产品包括具有NMOS栅极绝缘层的NMOS晶体管，具有大致矩形横截面构造的NMOS金属硅化物和位于NMOS金属硅化物区域上的NMOS金属层。该产品还包括具有相同栅极绝缘材料的PMOS晶体管，第一PMOS金属和PMOS金属硅化物区域，其中NMOS和PMOS金属硅化物区域由相同的金属硅化物组成。

45. 发明申请

US20160380076A1 METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE 有权
公开(公告)号：US20160380076A1
公开(公告)日：2016-12-29
申请号：US15258597
申请日：2016-09-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
发明人： Takashi Ando , Eduard A. Cartier , Kisik Choi , Vijay Narayanan
IPC分类号： H01L29/66 , H01L21/28 , H01L21/321
CPC分类号： H01L29/66545 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/28017 , H01L21/28088 , H01L21/32055 , H01L21/321 , H01L21/324 , H01L29/4232 , H01L29/66 , H01L29/66795 , H01L29/6681
摘要： A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

46. 发明授权

US09472643B2 Method to improve reliability of replacement gate device 有权
公开(公告)号：US09472643B2
公开(公告)日：2016-10-18
申请号：US14595756
申请日：2015-01-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
发明人： Takashi Ando , Eduard A. Cartier , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/3205 , H01L29/66 , H01L21/28 , H01L21/324 , H01L29/423 , H01L21/321
CPC分类号： H01L29/66545 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/28017 , H01L21/28088 , H01L21/32055 , H01L21/321 , H01L21/324 , H01L29/4232 , H01L29/66 , H01L29/66795 , H01L29/6681
摘要： A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

47. 发明申请

US20160099333A1 FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION 审中-公开
公开(公告)号：US20160099333A1
公开(公告)日：2016-04-07
申请号：US14967797
申请日：2015-12-14
申请人： GLOBALFOUNDRIES INC.
发明人： Hoon Kim , Kisik Choi , Chanro Park
IPC分类号： H01L29/49 , H01L29/78
CPC分类号： H01L29/4966 , H01L21/28008 , H01L21/28088 , H01L21/28194 , H01L29/4236 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.

48. 发明申请

US20150263120A1 REPLACEMENT GATE STRUCTURE WITH LOW-K SIDEWALL SPACER FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的低K侧壁间隔件的更换门结构
公开(公告)号：US20150263120A1
公开(公告)日：2015-09-17
申请号：US14725392
申请日：2015-05-29
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruilong Xie , Kisik Choi
IPC分类号： H01L29/51
CPC分类号： H01L29/512 , H01L21/02164 , H01L21/0217 , H01L21/28114 , H01L21/31111 , H01L21/32133 , H01L21/32139 , H01L21/76897 , H01L23/485 , H01L29/42372 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66628 , H01L29/78
摘要： One method and device disclosed includes, among other things, forming a recessed sacrificial gate electrode having a recessed upper surface, performing at least one second etching process to define recessed sidewall spacers positioned adjacent the recessed sacrificial gate electrode, forming a plurality of sidewall spacers within a gate opening above the recessed sidewall spacers, wherein one of the spacers comprises a low-k insulating material that is positioned laterally between two other spacers and a gate cap layer, removing the recessed sacrificial gate electrode and forming a replacement gate structure in its place.
摘要翻译：所公开的一种方法和装置尤其包括形成具有凹陷的上表面的凹陷的牺牲栅极电极，执行至少一个第二蚀刻工艺以限定邻近凹陷的牺牲栅电极定位的凹陷的侧壁间隔件，在其内形成多个侧壁间隔件在凹陷的侧壁间隔物上方的门开口，其中一个间隔件包括位于两个其它间隔件和栅极帽层之间横向定位的低k绝缘材料，去除凹陷的牺牲栅电极并在其位置形成替换栅极结构。

49. 发明申请

US20150236135A1 METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE 有权
公开(公告)号：US20150236135A1
公开(公告)日：2015-08-20
申请号：US14699427
申请日：2015-04-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
发明人： Takashi Ando , Eduard A. Cartier , Kisik Choi , Vijay Narayanan
IPC分类号： H01L29/66 , H01L21/28 , H01L21/02 , H01L21/324
CPC分类号： H01L29/66545 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/28017 , H01L21/28088 , H01L21/32055 , H01L21/321 , H01L21/324 , H01L29/4232 , H01L29/66 , H01L29/66795 , H01L29/6681
摘要： A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

50. 发明授权

US09105497B2 Methods of forming gate structures for transistor devices for CMOS applications 有权
标题翻译：为CMOS应用形成晶体管器件的栅极结构的方法
公开(公告)号：US09105497B2
公开(公告)日：2015-08-11
申请号：US14017485
申请日：2013-09-04
申请人： GLOBALFOUNDRIES Inc.
发明人： Zhendong Hong , Susie Tzeng , Amol Joshi , Ashish Bodke , Divya Pisharoty , Usha Raghuram , Olov Karlsson , Kisik Choi , Salil Mujumdar , Paul R. Besser , Jinping Liu , Hoon Kim
IPC分类号： H01L21/28 , H01L27/092 , H01L29/51 , H01L29/66 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/28097 , H01L21/28185 , H01L21/28194 , H01L21/823835 , H01L27/092 , H01L29/4975 , H01L29/517 , H01L29/66545
摘要： One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.
摘要翻译：用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层，在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及在NMOS和PMOS门腔内形成栅极盖层。

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