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41. 发明授权

US07760010B2 Switched-capacitor charge pumps 有权
标题翻译：开关电容充电泵
公开(公告)号：US07760010B2
公开(公告)日：2010-07-20
申请号：US11927784
申请日：2007-10-30
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： G05F1/46 , H02M3/18
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4074 , G11C2207/104
摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.
摘要翻译：开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。提供负电荷泵和正电荷泵实施例。充电电路有利地利用非重叠的宽和窄的时钟信号来产生多个门控信号。泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。

42. 发明授权

US07545690B2 Method for evaluating memory cell performance 失效
标题翻译：评估存储单元性能的方法
公开(公告)号：US07545690B2
公开(公告)日：2009-06-09
申请号：US11741187
申请日：2007-04-27
申请人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

43. 发明申请

US20080273403A1 STORAGE CELL DESIGN EVALUATION CIRCUIT INCLUDING A WORDLINE TIMING AND CELL ACCESS DETECTION CIRCUIT 失效
标题翻译：存储单元设计评估电路，包括WORDLINE时序和细胞检测电路
公开(公告)号：US20080273403A1
公开(公告)日：2008-11-06
申请号：US12125011
申请日：2008-05-21
申请人： Sebastian Ehrenreich , Jente B. Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B. Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路提供关于静态存储单元中的状态变化的精确信息。存储单元测试行包括访问检测电路，其在与阵列中的其他单元的访问操作期间提供相同的负载。访问检测电路提供可以探测的输出，而不影响单元的定时，读取稳定性或可写性。测试行可以测试行的时钟和/或地址时序，并且可以包括用于行字线驱动器的单独的电源轨，从而可以确定访问时序，读取稳定性和可写入性与字线强度/访问电压的变化。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

44. 发明授权

US08588009B2 Circuit for memory cell recovery 失效
标题翻译：用于记忆细胞恢复的电路
公开(公告)号：US08588009B2
公开(公告)日：2013-11-19
申请号：US13247362
申请日：2011-09-28
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Carl J. Radens
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Carl J. Radens
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/02 , G11C7/04 , G11C11/417 , G11C11/419
摘要： An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit lines. The memory cell may be read through the bit lines to a sense amplifier, the transistors on the bit lines are subsequently deactivated and the transistors on the alternate paths are activated to write transposed bit values to the memory cell, thereby reversing the biases.
摘要翻译：一种用于抵抗存储单元中偏置温度不稳定性（BTI）的影响的装置和方法。连接到存储器单元的位线包含两个交替的交替路径，以将第一位线的下部连接到第二位线的上部，并且将第二位线的下部连接到第二位线的上部第一个位线。在位线上激活晶体管以读取和写入存储器单元的替代方案是替代路径上的晶体管可被激活以从相对的位线读取和写入存储器单元。存储器单元可以通过位线读取到读出放大器，位线上的晶体管随后被去激活，并且激活交替路径上的晶体管以将转置的位值写入存储器单元，从而反转偏置。

45. 发明申请

US20100257492A1 ON-CHIP LEAKAGE CURRENT MODELING AND MEASUREMENT CIRCUIT 有权
标题翻译：片内泄漏电流建模和测量电路
公开(公告)号：US20100257492A1
公开(公告)日：2010-10-07
申请号：US12419377
申请日：2009-04-07
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
IPC分类号： G06F17/50 , G01R19/00
CPC分类号： G01R31/025 , G11C29/006 , G11C29/028 , G11C29/50 , G11C2029/5006 , G11C2029/5602
摘要： A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
摘要翻译：泄漏电流监测电路在集成在管芯上的数字电路中提供精确的统计代表性的真实截止漏电流的模拟。与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流，类型设备已超过阈值。测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。

46. 发明授权

US07408829B2 Methods and arrangements for enhancing power management systems in integrated circuits 有权
标题翻译：集成电路中增强电源管理系统的方法和安排
公开(公告)号：US07408829B2
公开(公告)日：2008-08-05
申请号：US11352699
申请日：2006-02-13
申请人： Jente B. Kuang , Hung Cai Ngo
发明人： Jente B. Kuang , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.
摘要翻译：本文提供了为集成电路配置电源管理系统的方法和布置。功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

47. 发明申请

US20080130387A1 METHOD FOR EVALUATING MEMORY CELL PERFORMANCE 失效
标题翻译：评估记忆体性能的方法
公开(公告)号：US20080130387A1
公开(公告)日：2008-06-05
申请号：US11741187
申请日：2007-04-27
申请人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

48. 发明授权

US5872733A Ramp-up rate control circuit for flash memory charge pump 失效
标题翻译：闪存充电泵的升压速率控制电路
公开(公告)号：US5872733A
公开(公告)日：1999-02-16
申请号：US730628
申请日：1996-10-21
申请人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary Joseph Saccamango , Hyun Jong Shin
发明人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary Joseph Saccamango , Hyun Jong Shin
IPC分类号： G11C16/30 , H03K5/04 , H03F3/16 , H03L7/00
CPC分类号： G11C16/30 , H03K5/04
摘要： An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor. The flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. Other embodiments of the apparatus of the present invention are described herein.
摘要翻译：一种用于控制具有提供输出电压和输出电流的输出的电荷泵的上升速率的装置。在一个实施例中，该装置包括具有输入，适于连接到地电势的输出和至少一个具有栅极，源极，漏极和主体的晶体管的电流泄放电路，并且限定源极和漏极之间的至少一个电流路径形成输入和输出之间的当前路径。主体适用于连接到电荷泵输出。该装置还包括具有适于连接到电荷泵输出的输入端的控制电路和连接到泄放电路输入端的输出端。控制电路为电流放电电路的输入提供电压电位，以控制电流放电电路晶体管的栅极 - 源极电压。通过电流泄放路径的电流路径的电流流动是电荷泵输出的大小和泄放电路晶体管的栅极 - 源极电压的函数。本文描述了本发明装置的其它实施例。

49. 发明授权

US08526256B2 Single-ended sense amplifier with read-assist 失效
标题翻译：具有读取辅助功能的单端读出放大器
公开(公告)号：US08526256B2
公开(公告)日：2013-09-03
申请号：US13234218
申请日：2011-09-16
申请人： Amlan Ghosh , Jente B. Kuang
发明人： Amlan Ghosh , Jente B. Kuang
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C7/067
摘要： A sense amplifier is provided that comprises, responsive to receiving a set signal to turn on a set device and a precharged voltage level read bit line signal, a keeper device that turns on responsive to receiving a LOW signal from an inverting amplifier and pulls up the voltage at a first node so that a HIGH signal is output onto a global bit line. Responsive to receiving the set signal to turn on the set device and a read bit line signal that is discharging through a read stack path to ground and responsive to the read bit line signal discharging below a first predesigned voltage level, a read assist device in the sense amplifier turns on responsive to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW state is output onto a global bit line.
摘要翻译：提供了一种读出放大器，其包括响应于接收到设置信号以打开设备设备和预充电电压电平读取位线信号，保持器设备响应于从反相放大器接收低电平信号而接通，并且将上拉电压在第一节点处，使得HIGH信号被输出到全局位线。响应于接收所设置的信号以使所述设置装置和读取的位线信号通过读取堆叠路径放电到地并且响应于读取位线信号放电低于第一预先设计的电压电平，读取辅助装置在读出放大器响应于从反相放大器接收到高电平信号并且降低第一节点处的电压而导通，使得LOW状态输出到全局位线。

50. 发明授权

US08493774B2 Performing logic functions on more than one memory cell within an array of memory cells 失效
标题翻译：在存储单元阵列内的多个存储单元上执行逻辑功能
公开(公告)号：US08493774B2
公开(公告)日：2013-07-23
申请号：US13162753
申请日：2011-06-17
申请人： Jente B. Kuang , Rahul M. Rao
发明人： Jente B. Kuang , Rahul M. Rao
IPC分类号： G11C11/00
CPC分类号： G11C7/1006 , G11C11/412
摘要： A circuit structure is provided for performing a logic function within a memory. A plurality of read word line transistors are provided that receive a read word line signal and, upon receiving the read word line signal, the plurality of read word line transistors provide a path from a plurality of bit-line transistors associated with a plurality of physically adjacent memory cells to a read bit-line. In response to an associated memory cell within the memory storing a first value, each of the plurality of read bit-line transistors turns on and provides a path to ground thereby causing a first output value to be output on the read bit-line. In response to all of the plurality of memory cells storing a second value, the plurality of read bit-line transistors turn off thereby preventing a path to ground and a second output value is output on the read bit-line.
摘要翻译：提供了用于在存储器内执行逻辑功能的电路结构。提供了多个读取字线晶体管，其接收读取的字线信号，并且在接收到读取的字线信号时，多个读取字线晶体管提供了与多个物理上相关联的多个位线晶体管的路径相邻存储器单元到读位线。响应于存储器存储第一值的存储器单元，多个读取位线晶体管中的每一个导通并提供到地的路径，从而在读位线上输出第一输出值。响应于存储第二值的所有多个存储单元，多个读位线晶体管关闭，从而防止接地的路径，并在读位线上输出第二输出值。

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