专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08188521B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08188521B2
公开(公告)日：2012-05-29
申请号：US12728823
申请日：2010-03-22
申请人： Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/739 , H01L29/78 , H01L29/08
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0626 , H01L29/0634 , H01L29/0657 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/7808 , H01L29/7811 , H01L29/7828
摘要： A power semiconductor device has semiconductor layers, including: first layer of first type; second and third layers respectively of first and second types alternately on the first layer; fourth layers of second type on the third layers; fifth layers of first type on the fourth layer; sixth and seventh layers respectively of second and first types alternately on the second and third layers; a first electrode connected to the first layer; an insulation film on fourth, sixth, and seventh layers; a second electrode on fourth, sixth, and seventh layers via the insulation film; and a third electrode joined to fourth and fifth layers, wherein the sixth layers are connected to the fourth layers and one of the third layers between two fourth layers, and an impurity concentration of the third layers below the sixth layers is higher than that of the third layers under the fourth layers.
摘要翻译：功率半导体器件具有半导体层，包括：第一层第一层; 第一和第二类型的第二和第三层交替地在第一层上; 第三层第四层第四层; 第四层第五层第一层; 第二层和第三层的第六层和第七层交替地在第二层和第三层上; 连接到第一层的第一电极; 第四层，第六层和第七层的绝缘膜; 经由绝缘膜的第四，第六和第七层上的第二电极; 以及连接到第四和第五层的第三电极，其中第六层连接到第四层，第二层之间的第三层之间的第二层之间的第二层和第三层之间的第三层的杂质浓度高于第六层的第三层第四层第三层。

42. 发明授权

US08058688B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08058688B2
公开(公告)日：2011-11-15
申请号：US11864101
申请日：2007-09-28
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L31/119
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A semiconductor device includes: a semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a major surface of the semiconductor substrate and having lower doping concentration than the semiconductor substrate; a plurality of first semiconductor column regions of the first conductivity type provided on the first semiconductor layer; a plurality of second semiconductor column regions of a second conductivity type provided on the first semiconductor layer, the second semiconductor column regions being adjacent to the first semiconductor column regions; a first semiconductor region; a second semiconductor region; a gate insulating film; a first main electrode; a second main electrode; and a control electrode. Doping concentrations in both the first and second semiconductor column region are low on the near side of the first semiconductor layer and high on the second main electrode side.
摘要翻译：半导体器件包括：半导体衬底; 第一导电类型的第一半导体层设置在半导体衬底的主表面上并且具有比半导体衬底低的掺杂浓度; 设置在第一半导体层上的多个第一导电类型的第一半导体柱区域; 设置在所述第一半导体层上的第二导电类型的多个第二半导体柱区域，所述第二半导体柱区域与所述第一半导体柱区域相邻; 第一半导体区域; 第二半导体区域; 栅极绝缘膜; 第一主电极; 第二主电极; 和控制电极。第一和第二半导体柱区域中的掺杂浓度在第一半导体层的近侧为低，在第二主电极侧为高。

43. 发明授权

US07812392B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07812392B2
公开(公告)日：2010-10-12
申请号：US12138875
申请日：2008-06-13
申请人： Wataru Saito , Syotaro Ono
发明人： Wataru Saito , Syotaro Ono
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741
摘要： A semiconductor device includes a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a horizontal direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer, and a sixth semiconductor layer located outside and adjacent to the periodic array structure of the second first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and having a lower impurity concentration than the periodic array structure. The amount of impurity in the outermost semiconductor layer of the first conductivity type or the second conductivity type adjacent to the sixth semiconductor layer in the periodic array structure is generally half the amount of impurity in the second first-conductivity-type semiconductor layer or the third second-conductivity-type semiconductor layer inside the outermost semiconductor layer.
摘要翻译：半导体器件包括第一第一导电型半导体层，设置在第一第一导电型半导体层的主表面上的第二第一导电型半导体层; 与所述第二第一导电型半导体层相邻的第三第二导电型半导体层，设置在所述第一第一导电型半导体层的主表面上，并且与所述第二第一导电型半导体层的第二第一导电型半导体层在与第一第一导电型半导体层的主表面大致平行的水平方向上的第一导电型半导体层以及与第二第一导电型半导体的周期性阵列结构的外侧相邻的第六半导体层层和第三第二导电型半导体层，设置在第一第一导电型半导体层的主表面上，并且具有比周期性阵列结构低的杂质浓度。在周期性排列结构中与第六半导体层相邻的第一导电类型或第二导电类型的最外半导体层中的杂质的量通常为第二第一导电型半导体层或第三导电型半导体层中杂质的量的一半第二导电型半导体层。

44. 发明授权

US07800175B2 Vertical power semiconductor device with high breakdown voltage corresponding to edge termination and device regions 失效
标题翻译：具有高击穿电压的垂直功率半导体器件对应于边缘终端和器件区域
公开(公告)号：US07800175B2
公开(公告)日：2010-09-21
申请号：US12243280
申请日：2008-10-01
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/404
摘要： A semiconductor apparatus includes: a semiconductor layer of a first conductivity type; a first main electrode provided on a frontside of the semiconductor layer; a second main electrode provided on a backside of the semiconductor layer, the backside being opposite to the frontside; a plurality of semiconductor regions of a second conductivity type provided in a surface portion of the semiconductor layer in a edge termination region outside a device region in which a main current path is formed in a vertical direction between the first main electrode and the second main electrode; and a plurality of buried semiconductor regions of the second conductivity type provided in the semiconductor layer in the edge termination region, spaced from the semiconductor regions, and spaced from each other. The buried semiconductor regions provided substantially at the same depth from the frontside of the semiconductor layer are numbered as first, second, . . . , n-th, sequentially from the one nearer to the device region, the n-th buried semiconductor regions provided at different depths from the frontside of the semiconductor layer are displaced toward the device region relative to the corresponding n-th semiconductor region, and the buried semiconductor region located deeper from the frontside of the semiconductor layer is displaced more greatly toward the device region.
摘要翻译：半导体装置包括：第一导电类型的半导体层; 设置在所述半导体层的前侧的第一主电极; 设置在所述半导体层的背面的第二主电极，所述背面与所述前侧相反; 在第一主电极和第二主电极之间沿垂直方向形成有主电流路径的器件区域外的边缘终端区域的半导体层的表面部分中设置的多个第二导电类型的半导体区域 ; 以及设置在边缘终端区域中的半导体层中的与半导体区域间隔开并且彼此间隔开的第二导电类型的多个掩埋半导体区域。基本上与半导体层的前侧相同的深度设置的掩埋半导体区域被编号为第一，第二。。。第n个从靠近器件区的一个顺序地，与半导体层的前侧不同的深度设置的第n个埋入半导体区域相对于相应的第n个半导体区域朝向器件区域移位，位于半导体层的前侧较深的掩埋半导体区域朝向器件区域更大地移位。

45. 发明申请

US20080017897A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080017897A1
公开(公告)日：2008-01-24
申请号：US11668861
申请日：2007-01-30
申请人： Wataru SAITO , Syotaro Ono
发明人： Wataru SAITO , Syotaro Ono
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/7802 , H01L23/3192 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/4238 , H01L29/66712 , H01L29/66719 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a plurality of first semiconductor pillar regions of the first conductivity type provided on a major surface of the semiconductor layer; a plurality of second semiconductor pillar regions of a second conductivity type being adjacent to the first semiconductor pillar regions; a first main electrode provided on a side opposite to the major surface of the semiconductor layer; a first semiconductor region of the second conductivity type provided on the second semiconductor pillar regions; a second semiconductor region of the first conductivity type provided in a surface portion of the first semiconductor region; a second main electrode provided on the second semiconductor region; a trench being adjacent to the first semiconductor region and the second semiconductor region and reaching the first semiconductor pillar region from the surface side of the second semiconductor region; an insulating film provided on an inner wall surface of the trench; and a control electrode buried inside the trench via the insulating film. The doping concentration in the vertical direction at the center of the width of the second semiconductor pillar region is substantially constant up to a substantially intermediate portion in the direction from the second main electrode toward the first main electrode and gradually decreases from the substantially intermediate portion toward the first main electrode.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的多个第一导电类型的第一半导体柱区域; 多个与第一半导体柱区相邻的第二导电类型的第二半导体柱区; 设置在与所述半导体层的主表面相对的一侧的第一主电极; 设置在第二半导体柱区上的第二导电类型的第一半导体区; 设置在第一半导体区域的表面部分中的第一导电类型的第二半导体区域; 设置在所述第二半导体区域上的第二主电极; 与第一半导体区域和第二半导体区域相邻并从第二半导体区域的表面侧到达第一半导体柱区域的沟槽; 设置在所述沟槽的内壁表面上的绝缘膜; 以及通过绝缘膜埋在沟槽内的控制电极。在第二半导体柱区域的宽度的中心处的垂直方向上的掺杂浓度在从第二主电极朝向第一主电极的方向上到大致中间部分基本上恒定，并且从大致中间部分逐渐减小第一主电极。

46. 发明申请

US20070001194A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070001194A1
公开(公告)日：2007-01-04
申请号：US11476595
申请日：2006-06-29
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L29/74
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66712 , H01L29/7802 , H01L29/7806 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a pillar layer including first semiconductor pillars of a first conduction type and second semiconductor pillars of a second conduction type formed laterally, periodically and alternately. The first and second semiconductor pillars include a plurality of diffusion layers formed in a third semiconductor layer as coupled along the depth. The diffusion layers have lateral widths varied at certain periods along the depth. An average of the lateral widths of the diffusion layers in one certain period is made almost equal to another between different periods.
摘要翻译：半导体器件包括：柱层，其包括第一导电类型的第一半导体柱和第二导电类型的第二半导体柱，所述第二导电类型横向，周期性地和交替地形成。第一和第二半导体柱包括沿着深度耦合形成在第三半导体层中的多个扩散层。扩散层的横向宽度在沿深度的某些周期变化。在一定时间段内扩散层的横向宽度的平均值在不同周期之间几乎等于另一个。

47. 发明申请

US20130221426A1 ELECTRIC POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：电力半导体器件及其制造方法
公开(公告)号：US20130221426A1
公开(公告)日：2013-08-29
申请号：US13600616
申请日：2012-08-31
申请人： Wataru Saito , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Hiroaki Yamashita
发明人： Wataru Saito , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Hiroaki Yamashita
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66719 , H01L29/7802 , H01L29/7811
摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.
摘要翻译：电力半导体装置的制造方法包括以下处理。在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。在外延层的表面形成多个第二第二导电型杂质注入层。在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

48. 发明申请

US20120217555A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120217555A1
公开(公告)日：2012-08-30
申请号：US13357381
申请日：2012-01-24
申请人： Wataru SAITO , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
发明人： Wataru SAITO , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
IPC分类号： H01L29/772
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/42356 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7395
摘要： A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
摘要翻译：实施例的第一半导体器件包括第一导电类型的第一半导体层，第一控制电极，引出电极，第二控制电极和第三控制电极。第一控制电极通过第一绝缘膜面对第一导电类型的第二半导体层，第二导电类型的第三半导体层和第一导电类型的第四半导体层。第二控制电极和第三控制电极通过第二绝缘膜电连接到引出电极，并且与提取电极下方的第二半导体层相对。第二控制电极和整个第三控制电极的至少一部分设置在引出电极的下方。第二控制电极的电阻高于第三控制电极的电阻。

49. 发明申请

US20110215418A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110215418A1
公开(公告)日：2011-09-08
申请号：US13029925
申请日：2011-02-17
申请人： Wataru SAITO , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
发明人： Wataru SAITO , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
IPC分类号： H01L27/07 , H01L29/72
CPC分类号： H01L27/07 , H01L29/72
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region. A distance between the embedded semiconductor region and the second major surface along a direction from the second major surface toward the first major surface becomes longer toward outside from the device region.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第一导电类型的第二半导体区域，第一主电极，第二导电类型的第三半导体区域，第二主电极和多个第二导电类型的嵌入式半导体区域。第二半导体区域形成在第一半导体区域的第一主表面上。第一主电极形成在与第一半导体区域的第一主表面相对的正面上。第三半导体区域形成在第二半导体区域的与第一半导体区域相对的一侧的第二主表面上。第二主电极形成为结合到第三半导体区域。嵌入式半导体区域设置在终端区域中。沿着从第二主表面朝向第一主表面的方向在嵌入式半导体区域和第二主表面之间的距离从器件区域向外部变长。

50. 发明授权

US07759733B2 Power semiconductor device and method for producing the same 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US07759733B2
公开(公告)日：2010-07-20
申请号：US12055585
申请日：2008-03-26
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A power semiconductor device includes: a first semiconductor substrate; a second semiconductor layer; a plurality of third semiconductor pillar regions and a plurality of fourth semiconductor pillar regions that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor substrate; a first main electrode; and a second main electrode. A concentration of first-conductivity-type impurity in a connective portion between the second semiconductor layer and the third semiconductor pillar regions is lower than concentrations of first-conductivity-type impurity in portions of both sides of the connective portion in a direction from the second semiconductor layer to the third semiconductor pillar regions.
摘要翻译：功率半导体器件包括：第一半导体衬底; 第二半导体层; 多个第三半导体柱区域和多个第四半导体柱区域，其设置在所述第二半导体层的上层中，并且沿着与所述第一半导体衬底的上表面平行的方向交替布置; 第一主电极; 和第二主电极。在第二半导体层和第三半导体柱区域之间的连接部分中的第一导电型杂质的浓度低于第二导电类型杂质在连接部分的两侧部分中的浓度半导体层到第三半导体柱区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式