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41. 发明申请

US20050128843A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20050128843A1
公开(公告)日：2005-06-16
申请号：US10983617
申请日：2004-11-09
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
IPC分类号： H01L21/3205 , H01L21/8247 , H01L23/52 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/7881 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.
摘要翻译：根据本发明的非易失性半导体存储器包括：存储单元单元，其包括彼此并联形成的数据选择线，与数据选择线相交并且彼此并联排列的数据传输线;以及电可重写存储单元晶体管，数据传输线和数据选择线的交点。它还包括：存储单元阵列块，其中存储单元单元沿数据选择线设置; 第一源极线，连接到存储单元单元的一端，并沿数据选择线对齐; 以及第二源极线，其电连接到第一源极线，并且沿着数据选择线布置。

42. 发明申请

US20050093125A1 Semiconductor device, electronic card and pad rearrangement substrate 失效
标题翻译：半导体器件，电子卡和衬垫重排衬底
公开(公告)号：US20050093125A1
公开(公告)日：2005-05-05
申请号：US11005438
申请日：2004-12-06
申请人： Minori Kajimoto , Osamu Ikeda , Masaki Momodomi
发明人： Minori Kajimoto , Osamu Ikeda , Masaki Momodomi
IPC分类号： B42D15/10 , G06K19/07 , G06K19/077 , H01L23/12 , H01L23/498 , H01L23/02
CPC分类号： H01L23/49855 , G06K19/077 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05599 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/484 , H01L2224/49171 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device comprises a substrate, an external terminal provided on the substrate, an internal wiring pattern electrically connected to the external terminal, a semiconductor chip mounted on the substrate and electrically connected to the internal wiring pattern, and an antenna pattern. The antenna pattern provided at each of adjacent two corner portions of the substrate and is grounded.
摘要翻译：半导体器件包括衬底，设置在衬底上的外部端子，与外部端子电连接的内部布线图案，安装在衬底上并电连接到内部布线图案的半导体芯片和天线图案。天线图案设置在基板的相邻两个角部的每一个处并接地。

43. 发明授权

US08592885B2 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08592885B2
公开(公告)日：2013-11-26
申请号：US13365470
申请日：2012-02-03
申请人： Shigeru Kinoshita , Hisataka Meguro , Minori Kajimoto
发明人： Shigeru Kinoshita , Hisataka Meguro , Minori Kajimoto
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28273 , H01L29/42336 , H01L29/66825
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括衬底，隧道绝缘膜，浮动栅极，泄漏抑制单元，栅极间绝缘膜和控制栅极。衬底包括硅。隧道绝缘膜设置在基板上。浮动栅极设置在隧道绝缘膜上。泄漏抑制单元设置在浮动栅极上。栅极间绝缘膜设置在泄漏抑制单元上。控制栅极设置在栅极间绝缘膜上。泄漏抑制单元的介电常数高于栅极间绝缘膜的介电常数。

44. 发明授权

US08253182B2 Nonvolatile semiconductor memory and method for fabricating the same 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US08253182B2
公开(公告)日：2012-08-28
申请号：US12588203
申请日：2009-10-07
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

45. 发明授权

US08207560B2 Nonvolatile semiconductor memory device and method of fabricating the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08207560B2
公开(公告)日：2012-06-26
申请号：US11873104
申请日：2007-10-16
申请人： Minori Kajimoto
发明人： Minori Kajimoto
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S257/90
摘要： A nonvolatile semiconductor memory device includes a gate electrode formed on a gate insulating film, a source/drain region formed at each side of the gate electrode and including a first region, a second region and a third region located between the first and second regions, a first silicon oxide film formed on a sidewall of the gate electrode, a second silicon oxide film formed on the third region, and a silicon nitride film formed on an upper surface of the second silicon oxide film. The first silicon oxide film, the second silicon oxide film having the silicon nitride film, and a contact plug are contiguously arranged on the first, third and second regions of the source/drain region. The contact plug extends through the second silicon oxide film and the second nitride file to contact the source/drain region.
摘要翻译：非易失性半导体存储器件包括形成在栅极绝缘膜上的栅电极，形成在栅电极的每一侧的源极/漏极区，并且包括位于第一和第二区之间的第一区，第二区和第三区，形成在栅电极的侧壁上的第一氧化硅膜，形成在第三区域上的第二氧化硅膜和形成在第二氧化硅膜的上表面上的氮化硅膜。第一氧化硅膜，具有氮化硅膜的第二氧化硅膜和接触插塞被连续排列在源极/漏极区域的第一，第三和第二区域上。接触插塞延伸穿过第二氧化硅膜和第二氮化物文件以接触源极/漏极区域。

46. 发明授权

US07948053B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07948053B2
公开(公告)日：2011-05-24
申请号：US12423914
申请日：2009-04-15
申请人： Yugo Ide , Minori Kajimoto
发明人： Yugo Ide , Minori Kajimoto
IPC分类号： H01L29/00
CPC分类号： H01L27/11546 , H01L27/11526 , H01L28/20
摘要： A semiconductor device includes a first insulating film, paired resistance elements each of which includes a first conductive film formed on the first insulating film, a second insulating film formed on the first conductive film and a second conductive film formed on the second insulating film, paired first contact plugs formed on one of the resistance elements and arranged along a first direction, and paired second contact plugs formed on the other resistance. One of the resistance elements has a first width in a second direction perpendicular to the first direction, and a semiconductor region surrounded by an element isolation region has a second width. The first width is smaller than half of the second width. The second insulating films are spaced from each other by a first distance. The second conductive films are spaced from each other by a second distance. The second distance is longer than the first distance.
摘要翻译：半导体器件包括第一绝缘膜，成对电阻元件，每个电阻元件包括形成在第一绝缘膜上的第一导电膜，形成在第一导电膜上的第二绝缘膜和形成在第二绝缘膜上的第二导电膜，成对形成在一个电阻元件上并沿着第一方向布置的第一接触插塞和形成在另一个电阻上的成对的第二接触插塞。电阻元件中的一个在垂直于第一方向的第二方向上具有第一宽度，并且由元件隔离区域包围的半导体区域具有第二宽度。第一宽度小于第二宽度的一半。第二绝缘膜彼此隔开第一距离。第二导电膜彼此隔开第二距离。第二距离比第一距离长。

47. 发明授权

US07800154B2 Nonvolatile semiconductor memory device with twin-well 有权
标题翻译：具有双阱的非易失性半导体存储器件
公开(公告)号：US07800154B2
公开(公告)日：2010-09-21
申请号：US11031036
申请日：2005-01-10
申请人： Mitsuhiro Noguchi , Minori Kajimoto
发明人： Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L29/94
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526
摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.
摘要翻译：非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱，其包括围绕所述第一阱的侧部区域的第一部分和围绕所述第一阱的下部区域的第二部分，并且将所述第一阱与所述半导体衬底以及所述第二导电类型的第三阱电隔离，其形成在半导体衬底中。第三井具有比第二井的第二部分更少的深度。

48. 发明申请

US20090298254A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20090298254A1
公开(公告)日：2009-12-03
申请号：US12541457
申请日：2009-08-14
申请人： Haruhiko KOYAMA , Mitsuhiro Noguchi , Minori Kajimoto
发明人： Haruhiko KOYAMA , Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L21/30
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.
摘要翻译：在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。第一开口被配置为对准标记。第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。

49. 发明申请

US20090278190A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20090278190A1
公开(公告)日：2009-11-12
申请号：US12457704
申请日：2009-06-18
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
IPC分类号： H01L27/112 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/7881 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.
摘要翻译：根据本发明的非易失性半导体存储器包括：存储单元单元，其包括彼此并联形成的数据选择线，与数据选择线相交并且彼此并联排列的数据传输线;以及电可重写存储单元晶体管，数据传输线和数据选择线的交点。它还包括：存储单元阵列块，其中存储单元单元沿数据选择线设置; 第一源极线，连接到存储单元单元的一端，并沿数据选择线对齐; 以及第二源极线，其电连接到第一源极线，并且沿着数据选择线设置。

50. 发明授权

US07585742B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07585742B2
公开(公告)日：2009-09-08
申请号：US11536291
申请日：2006-09-28
申请人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
发明人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.
摘要翻译：在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。第一开口被配置为对准标记。第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。

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