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    • 42. 发明授权
    • Piezoelectric diaphragm structure with outer edge electrode
    • 压电膜片结构,外缘电极
    • US07084555B2
    • 2006-08-01
    • US10739478
    • 2003-12-18
    • John R. BachellerieSteven A. BuhlerJohn S. FitchMeng H. LeanKarl A. Littau
    • John R. BachellerieSteven A. BuhlerJohn S. FitchMeng H. LeanKarl A. Littau
    • H01L41/08
    • H01L41/0973H01L41/047
    • A multi-electrode piezoelectric diaphragm structure includes a diaphragm, piezoelectric material located on the diaphragm, which is defined as having a first area, and a second area. The first area of the piezoelectric is poled in a first direction, and the second area of the piezoelectric is poled in a second direction. The poled first direction is in a Z-axis of the piezoelectric and the poled second direction is in a Radial axis of the piezoelectric. A first electrode is positioned in the first area, on the first surface, of the piezoelectric. A second electrode is positioned in the second area, on the first surface, of the piezoelectric. A third electrode is located on a second surface of the piezoelectric. The application of voltages to the first, second and third electrodes generates electric fields in the piezoelectric material resulting in actuation of the piezoelectric material, or the application of pressure or strain to the diaphragm generates electric potentials at the first, second and third electrodes.
    • 多电极压电膜结构包括隔膜,位于膜片上的压电材料,其被定义为具有第一区域,第二区域。 压电体的第一区域沿第一方向极化,并且压电体的第二区域在第二方向上极化。 极化的第一方向在压电体的Z轴上,并且极化的第二方向处于压电体的径向轴线。 第一电极位于压电体的第一表面的第一区域中。 第二电极位于压电体的第一表面的第二区域中。 第三电极位于压电体的第二表面上。 施加电压到第一,第二和第三电极在压电材料中产生电场,导致压电材料的致动,或施加压力或应变到隔膜在第一,第二和第三电极处产生电位。
    • 49. 发明授权
    • Wet micro-channel wafer chuck and cooling method
    • 湿式微通道晶片卡盘和冷却方式
    • US5203401A
    • 1993-04-20
    • US888040
    • 1992-05-22
    • William R. HamburgenJohn S. Fitch
    • William R. HamburgenJohn S. Fitch
    • G01R1/04
    • G01R1/0458Y10S165/917
    • A wet micro-channel wafer chuck (10) holds a semiconductor wafer 12 having a plurality of high powered chips (14) held in place with vacuum provided in the chuck (10). The chuck (10) has a plurality of micro-channels (16), which extend along cooling fins (18), on which the semiconductor wafer (12) rests when it is held in place on the chuck. A water supply manifold (20) extends perpendicular to the micro-channels (16) across the chuck (10). Water supply slot (22) extends upward from the water supply manifold into the micro-channels (16). Similarly, water exit slots (24) extend upward from water exit manifolds (26) into the micro-channels (16). Water (28) is delivered from pump (30) of an external recirculator/chiller (32) to the supply manifold (20) and into the many micro-channels (16) that pass under the wafer (12) under test. The water (28) leaves the micro-channels (16), enters the exit slots (24) and then the exit manifolds (26), from which it is returned to the recirculator/chiller (32). Reservoir or tank (34) of the recirculator/chiller (32) is connected to a regulated vacuum source (36). By applying a vacuum, the pressure in the cooling loop is lowered below atmospheric, and the wafer (12) under test is held against surface (38) of the chuck (10).
    • 湿式微通道晶片卡盘(10)将具有设置在卡盘(10)中的真空的多个高功率芯片(14)保持在适当位置的半导体晶片12。 卡盘(10)具有多个微通道(16),其沿着冷却翅片(18)延伸,当半导体晶片(12)保持在卡盘上的适当位置时,半导体晶片(12)停留在该多个微通道(16)上。 供水歧管(20)横跨卡盘(10)垂直于微通道(16)延伸。 供水槽(22)从供水歧管向上延伸到微通道(16)中。 类似地,出水槽(24)从出水歧管(26)向上延伸到微通道(16)中。 水(28)从外部再循环器/冷却器(32)的泵(30)输送到供给歧管(20)并进入通过待测晶片(12)下方的许多微通道(16)。 水(28)离开微通道(16),进入出口狭槽(24),然后进入出口歧管(26),从此返回到再循环/冷却器(32)。 再循环器/冷却器(32)的储存罐(34)与调节的真空源(36)连接。 通过施加真空,将冷却回路中的压力降低到低于大气压,并且将被测试的晶片(12)保持在卡盘(10)的表面(38)上。