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41. 发明授权

US07116088B2 High voltage shunt regulator for flash memory 有权
标题翻译：闪存高压分流调节器
公开(公告)号：US07116088B2
公开(公告)日：2006-10-03
申请号：US10457975
申请日：2003-06-09
申请人： Hieu Van Tran , Thuan T. Vu , Susmita Karmakar
发明人： Hieu Van Tran , Thuan T. Vu , Susmita Karmakar
IPC分类号： G05F1/40 , H02M3/18
CPC分类号： G05F3/30
摘要： A high shunt regulator provides precise voltage over process, temperature, power supply, and foundries. The HV level is settable by a digital control bits such as fuse bits. A filter network filters out the ripple noise and charge transient. A tracking capacitor divider network speeds up response time. A fractional band gap reference provides fractional bandgap voltage and current, and operates at low power supply and has superior power supply rejection. It is unsusceptible to substrate hot carrier effect. It exposes very little to drain induced barrier lowering effect. The bandgap core has better than conventional transient response and stability. One embodiment has adjustable level control. Complementary TC (temperature coefficient) trimming allows efficient realization of zero temperature coefficients of current and voltage. Higher order curvature correction of voltage and current is integrated. Replica bias for the control loop is presented. A Binary and Approximation Complementary TC search trimming is described. A zero TC fractional voltage less than the theoretical bandgap voltage (
摘要翻译：高分流稳压器提供精确的过程电压，温度，电源和铸造厂。 HV电平可由诸如保险丝位之类的数字控制位来设置。滤波器网络滤除纹波噪声和充电瞬变。跟踪电容分压网络可加快响应时间。分数带隙参考提供分数带隙电压和电流，并且在低电源下工作并具有优异的电源抑制。衬底热载体效应是不可察觉的。它暴露出很少的漏极引起的屏障降低效果。带隙核优于传统的瞬态响应和稳定性。一个实施例具有可调节的电平控制。互补TC（温度系数）修整可以有效地实现电流和电压的零温度系数。整合电压和电流的高阶曲率校正。提出了控制回路的复制偏差。描述了二进制和近似互补TC搜索修剪。小于理论带隙电压（<<〜1.2伏特）的零TC分数电压是可实现的。带隙芯具有抑制高频噪声的滤波机制。低功率启动电路加电带隙。带隙也具有可变阻抗。

42. 发明授权

US07149110B2 Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system 有权
标题翻译：寻求窗口验证程序系统和方法，用于多级非易失性存储器集成电路系统
公开(公告)号：US07149110B2
公开(公告)日：2006-12-12
申请号：US10737689
申请日：2003-12-15
申请人： Hieu Van Tran , Hung Q. Nguyen , Amitay Levi , Isao Nojima
发明人： Hieu Van Tran , Hung Q. Nguyen , Amitay Levi , Isao Nojima
IPC分类号： G11C11/34
CPC分类号： G11C13/0064 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2013/0054 , G11C2211/5634
摘要： A memory comprises a plurality of digital multilevel memory cells. A window of valid data voltages for accessing the said plurality of digital multilevel memory cells is detected. The window may be detected by incrementing a first programming voltage to program data in the plurality of memory cells and verifying whether the data in at least one of said plurality of memory cells is properly programmed. The incrementing and verifying may be repeated until data is verified to be properly programmed in one of said plurality of memory cells. The data in each memory cell of said plurality of memory cells is verified. The verification may be by incrementing a second programming voltage, and verifying whether data in each memory cell is properly programmed within a margin. The incrementing and verifying is repeated for each memory cell outside of the margin.
摘要翻译：存储器包括多个数字多电平存储器单元。检测用于访问所述多个数字多电平存储器单元的有效数据电压的窗口。可以通过将第一编程电压递增到多个存储器单元中的程序数据并且验证所述多个存储器单元中的至少一个中的数据是否被适当地编程来检测窗口。可以重复递增和验证直到数据被验证为在所述多个存储器单元之一中被适当地编程。验证所述多个存储单元的每个存储单元中的数据。验证可以通过增加第二编程电压，并验证每个存储器单元中的数据是否在一定的范围内被适当地编程。对边缘外的每个存储单元重复递增和验证。

43. 发明授权

US07019998B2 Unified multilevel cell memory 有权
标题翻译：统一的多层单元格内存
公开(公告)号：US07019998B2
公开(公告)日：2006-03-28
申请号：US10659226
申请日：2003-09-09
申请人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
发明人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
IPC分类号： G11C15/00
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.
摘要翻译：统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。数据或代码可以存储在单独的数组或公共数组中。在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。标记位可能表示通信接口或IO驱动程序类型。感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。统一存储器中包含XCAM（例如，CAM）阵列。包括统一内存并发。

44. 发明授权

US07336516B2 Unified multilevel memory systems and methods 有权
标题翻译：统一的多级内存系统和方法
公开(公告)号：US07336516B2
公开(公告)日：2008-02-26
申请号：US11229191
申请日：2005-09-15
申请人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
发明人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
IPC分类号： G11C15/00
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.
摘要翻译：统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。数据或代码可以存储在单独的数组或公共数组中。在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。标记位可能表示通信接口或IO驱动程序类型。感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。统一存储器中包含XCAM（例如，CAM）阵列。包括统一内存并发。

45. 发明授权

US07212459B2 Unified multilevel cell memory 有权
标题翻译：统一的多层单元格内存
公开(公告)号：US07212459B2
公开(公告)日：2007-05-01
申请号：US11126495
申请日：2005-05-10
申请人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
发明人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
IPC分类号： G11C7/02
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.
摘要翻译：统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。数据或代码可以存储在单独的数组或公共数组中。在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。标记位可能表示通信接口或IO驱动程序类型。感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。统一存储器中包含XCAM（例如，CAM）阵列。包括统一内存并发。

46. 发明申请

US20130148428A1 Non-volatile Memory Device And A Method Of Programming Such Device 有权
公开(公告)号：US20130148428A1
公开(公告)日：2013-06-13
申请号：US13315213
申请日：2011-12-08
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Thuan Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Thuan Vu
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C7/00 , G11C7/22 , G11C16/26 , G11C16/28 , G11C2207/2263 , G11C2211/5647 , H01L27/11517
摘要： A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

47. 发明申请

US20120074923A1 Fast Voltage Regulators For Charge Pumps 有权
标题翻译：用于充电泵的快速稳压器
公开(公告)号：US20120074923A1
公开(公告)日：2012-03-29
申请号：US13306950
申请日：2011-11-29
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F3/16
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

48. 发明申请

US20090160411A1 FAST VOLTAGE REGULATORS FOR CHARGE PUMPS 有权
标题翻译：充电泵的快速电压调节器
公开(公告)号：US20090160411A1
公开(公告)日：2009-06-25
申请号：US12340571
申请日：2008-12-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

49. 发明授权

US07276971B2 Multi-operational amplifier system 有权
公开(公告)号：US07276971B2
公开(公告)日：2007-10-02
申请号：US11652719
申请日：2007-01-11
申请人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin
发明人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F3/211 , H03F3/45183 , H03F3/45475 , H03F3/72 , H03F2203/21109 , H03F2203/21145 , H03F2203/45138 , H03F2203/45288 , H03F2203/45541 , H03F2203/45618 , H03F2203/45626 , H03F2203/45722 , H03F2203/45728 , H03F2203/7206 , H03F2203/7215
摘要： A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

50. 发明授权

US07236054B2 Multi-operational amplifier system 有权
公开(公告)号：US07236054B2
公开(公告)日：2007-06-26
申请号：US10767248
申请日：2004-01-28
申请人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin
发明人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F3/211 , H03F3/45183 , H03F3/45475 , H03F3/72 , H03F2203/21109 , H03F2203/21145 , H03F2203/45138 , H03F2203/45288 , H03F2203/45541 , H03F2203/45618 , H03F2203/45626 , H03F2203/45722 , H03F2203/45728 , H03F2203/7206 , H03F2203/7215
摘要： A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

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