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41. 发明授权

US07046573B2 Semiconductor integrated circuit and IC card 失效
公开(公告)号：US07046573B2
公开(公告)日：2006-05-16
申请号：US10748137
申请日：2003-12-31
申请人： Yoshio Takazawa , Toshio Yamada , Shinichi Ozawa , Takeo Kanai , Minoru Katoh , Koudou Yamauchi , Toshihiro Araki
发明人： Yoshio Takazawa , Toshio Yamada , Shinichi Ozawa , Takeo Kanai , Minoru Katoh , Koudou Yamauchi , Toshihiro Araki
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G11C7/12 , G11C7/22 , G11C17/12 , G11C2207/2227
摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

42. 发明授权

US07033452B2 Method for plugging a cell of a honeycomb structure and method for manufacturing a honeycomb plugged structure 有权
标题翻译：插入蜂窝结构体的电池的方法及蜂窝状堵塞结构体的制造方法
公开(公告)号：US07033452B2
公开(公告)日：2006-04-25
申请号：US10694998
申请日：2003-10-29
申请人： Toshio Yamada , Yasushi Noguchi
发明人： Toshio Yamada , Yasushi Noguchi
IPC分类号： B28B11/00 , C04B33/34
CPC分类号： B01D46/2418 , B01D46/2451 , B01D46/2466 , B01D2046/2492 , B28B11/006 , C04B38/0012
摘要： There are disclosed a method for plugging a cell of a honeycomb structure and a method for manufacturing a honeycomb plugged structure. By the methods, plug portion having arbitrary depth and/or shape can exactly and relatively easily be formed. There is disclosed the method for plugging cell 3 of a honeycomb structure 1 having a plurality of cells surrounded by partition walls and extending through an axial direction. In the method for plugging the cells of the honeycomb structure, plugging member 6 molded in predetermined shape is inserted into the cell 3, and the plugging member 6 is bonded to the peripheral partition walls 3 to form plug portions. There is also provided the method for manufacturing the honeycomb plugged structure, including the steps of: plugging at least a certain cells of the honeycomb structure by this plugging method.
摘要翻译：公开了一种堵塞蜂窝结构体的电池的方法和蜂窝状堵塞结构体的制造方法。通过该方法，可以精确且相对容易地形成具有任意深度和/或形状的插头部分。公开了一种蜂窝结构体1的封孔单元3的方法，该蜂窝结构体1具有被隔壁围绕并沿轴向延伸的多个单元。在将蜂窝结构体的细胞堵塞的方法中，将以规定形状成型的堵塞部件6插入电池3中，将封堵部件6接合在周边隔壁3上形成插头部。还提供了蜂窝状堵塞结构的制造方法，包括以下步骤：通过该堵塞方法堵塞蜂窝结构体的至少一部分细胞。

43. 发明授权

US06897496B2 Semiconductor device, a method of manufacturing the same and storage media 有权
标题翻译：半导体器件，其制造方法和存储介质
公开(公告)号：US06897496B2
公开(公告)日：2005-05-24
申请号：US09982839
申请日：2001-10-22
申请人： Toshio Yamada , Kazumasa Yanagisawa , Yoshihiro Shinozaki , Hidetomo Aoyagi
发明人： Toshio Yamada , Kazumasa Yanagisawa , Yoshihiro Shinozaki , Hidetomo Aoyagi
IPC分类号： H01L21/3205 , G11C5/02 , G11C5/06 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04 , H01L29/73
CPC分类号： G11C5/025 , G11C5/063
摘要： Outside-cell wiring that extends the upper part of a macro cell to the direction of X axis is composed of the wiring layer of the upper layer than a terminal for a signal of the macro cell and this terminal is formed to extend in the direction of Y axis (direction that intersects the direction of X axis) so that the outside-cell wiring can be secured for a plurality of wiring channels. The macro cell and the outside-cell wiring are connected via this signal terminal.
摘要翻译：将宏单元的上部延伸到X轴方向的外电池布线由与宏单元的信号的端子相比上层的布线层构成，该端子形成为沿着宏单元的方向延伸 Y轴（与X轴方向相交的方向），从而可以确保多个布线通道的外部单元布线。宏单元和外部单元布线通过该信号端子连接。

44. 再颁专利

USRE38647E1 Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：USRE38647E1
公开(公告)日：2004-11-09
申请号：US09945603
申请日：2001-09-04
申请人： Hiroyuki Yamauchi , Toshio Yamada
发明人： Hiroyuki Yamauchi , Toshio Yamada
IPC分类号： G01R1900
CPC分类号： G11C7/065 , H03K17/102 , H03K17/145
摘要： In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.

45. 发明授权

US06596666B1 Honeycomb structure 有权
标题翻译：蜂窝结构
公开(公告)号：US06596666B1
公开(公告)日：2003-07-22
申请号：US09710908
申请日：2000-11-14
申请人： Toshio Yamada
发明人： Toshio Yamada
IPC分类号： B01J2340
CPC分类号： B01J35/04 , F01N3/2828
摘要： A honeycomb structure includes multiple honeycomb segments joined by means of a bonding material. Each of the honeycomb segments has a plurality of passages which are defined by partition walls and extend in an axial direction, Flatness of outer walls to be joining planes of the honeycomb segments is 0.2 mm or more. The honeycomb structure is superior in durability, by which a honeycomb segment does not shift due to vibration or exhaust back pressure in use.
摘要翻译：蜂窝结构体包括通过接合材料接合的多个蜂窝段。每个蜂窝段具有由分隔壁限定并沿轴向延伸的多个通道，作为蜂窝段的接合面的外壁的平坦度为0.2mm以上。蜂窝结构体的耐久性优异，蜂窝片段在使用中由于振动或排气背压而不发生移动。

46. 发明授权

US06420042B1 Fe-based amorphous alloy thin strip with ultrathin oxide layer 有权
标题翻译：具有超薄氧化物层的Fe基非晶态合金薄带
公开(公告)号：US06420042B1
公开(公告)日：2002-07-16
申请号：US09405341
申请日：1999-09-24
申请人： Hiroaki Sakamoto , Toshio Yamada , Yoshiharu Inoue
发明人： Hiroaki Sakamoto , Toshio Yamada , Yoshiharu Inoue
IPC分类号： B32B1504
CPC分类号： B32B15/04 , B32B15/18 , C22C33/003 , C22C45/02 , Y10T428/12438
摘要： The present invention provides a low iron-loss Fe-based amorphous alloy thin strip having an ultrathin oxide layer with a controlled thickness and/or a segregated layer containing either or both P and S at the lower section of an ultrathin oxide layer, as well as an Fe-based amorphous alloy thin strip fabricated with an ultrathin oxide layer with a controlled structure on the thin strip surface, wherein the ultrathin oxide layer is formed with a two-layer structure on the thin strip surface to reduce iron loss. Specifically, there is provided an Fe-based amorphous alloy thin strip characterized by being a quenched metal thin strip obtained by ejecting a molten metal onto a moving substrate through a casting nozzle with a slot-shaped opening and quenching it to solidity, and by having ultrathin oxide layer with a thickness of from 5 nm to 20 nm on at least one surface of the thin strip. There is further provided an Fe-based amorphous alloy thin strip characterized by being a quenched metal thin strip obtained by ejecting a molten metal onto a moving substrate through a casting nozzle with a slot-shaped opening and quenching it to solidity, by having an ultrathin oxide layer on at least one surface of the thin strip, and by having a segregated layer containing either or both P and S at the lower section of the oxide layer.
摘要翻译：本发明提供一种低铁损Fe基非晶合金薄带，其具有在超薄氧化物层的下部具有受控厚度的超薄氧化物层和/或含有P和S两者或两者的分离层，以及作为在薄带表面上具有受控结构的超薄氧化物层制造的Fe基非晶态合金薄带，其中在薄带表面上形成具有两层结构的超薄氧化物层以减少铁损。具体地说，提供了一种Fe基非晶合金薄带，其特征在于：通过具有槽形开口的铸造喷嘴将熔融金属喷射到移动的基板上并淬火成固态而获得的淬火金属薄带，并且通过在薄带的至少一个表面上具有5nm至20nm厚度的超薄氧化物层。还提供了一种Fe基非晶合金薄带，其特征在于：通过具有槽形开口的铸造喷嘴将熔融金属喷射到移动的基板上并通过具有超薄在薄带的至少一个表面上的氧化物层，以及在氧化物层的下部具有含有P和S中的任一个或两者的偏析层。

47. 发明授权

US06390284B1 Hanging-down jig and overhead conveyor for motorcycle 失效
标题翻译：悬挂式夹具和摩托车架空输送机
公开(公告)号：US06390284B1
公开(公告)日：2002-05-21
申请号：US09573055
申请日：2000-05-18
申请人： Toshio Yamada , Toshihiro Tsuchiya , Norihisa Ohgi
发明人： Toshio Yamada , Toshihiro Tsuchiya , Norihisa Ohgi
IPC分类号： B65G1732
CPC分类号： B62D65/18
摘要： A hanging-down jig is provided for supporting a vehicle body frame for a motorcycle in a hung-down manner on a hanger of an overhead conveyor. A dummy frame is mounted on the vehicle body frame for the motorcycle for supporting the vehicle body frame in a hang-down manner on a support arm of the hanger of the overhead conveyor. The dummy frame includes a center member coupled to the vehicle body frame by a pin, and a pair of left and right side members coupled to the vehicle body frame by a pin. The angle of, the longitudinal positions of and the lateral distance between the side members with respect to the center member can be adjusted as desired. The longitudinal and vertical positions of a support portion provided on the support arm of the hanger and engaged with a hanging-down member of the dummy frame can be adjusted as desired.
摘要翻译：提供一种悬挂式夹具，用于以悬挂方式将机动车辆的车体框架支撑在架空输送机的悬挂架上。一个虚拟框架安装在用于摩托车的车身框架上，用于将悬架式车体框架以悬挂方式支撑在架空输送机的吊架的支撑臂上。虚拟框架包括通过销连接到车身框架的中心构件，以及通过销联接到车身框架的一对左侧和右侧构件。可以根据需要调整侧构件相对于中心构件的纵向位置和横向距离的角度。可以根据需要调节设置在衣架的支撑臂上并与虚拟框架的下垂构件接合的支撑部分的纵向和垂直位置。

48. 发明授权

US06285723B1 Timing signal generation circuit 失效
标题翻译：定时信号发生电路
公开(公告)号：US06285723B1
公开(公告)日：2001-09-04
申请号：US09513714
申请日：2000-02-25
申请人： Toshio Yamada , Masashi Agata
发明人： Toshio Yamada , Masashi Agata
IPC分类号： H04L700
CPC分类号： G06F1/04 , G06F1/10 , H03K5/131 , H03K5/133 , H03K5/135 , H03K2005/00052 , H03K2005/00286
摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.
摘要翻译：根据本发明的定时信号产生电路包括：延迟电路，用于在延迟时钟信号的同时传输输入时钟信号，延迟电路具有多个中间抽头，能够在延迟电路的相应位置输出时钟信号 ; 用于在延迟时钟信号的同时发送时钟信号的检测延迟电路，所述检测延迟电路具有能够在其检测延迟电路中的相应位置处输出时钟信号的多个中间抽头; 多个采样/保持电路，每个采样/保持电路均具有采样信号端子，采样信号端子连接到检测延迟电路的多个中间抽头中的相应的一个; 用于检测时钟信号的边沿的多个边界延迟电路，边界检测电路连接到取样/保持电路的各个输出端; 以及输出选择电路，用于经由根据由边界检测电路检测的时钟信号的边缘位置选择的多个中间抽头中的至少一个提取时钟信号，输出选择电路将提取的时钟信号作为定时输出信号。

49. 发明授权

US5979507A Gas flow pass 失效
标题翻译：气体流通
公开(公告)号：US5979507A
公开(公告)日：1999-11-09
申请号：US788844
申请日：1997-01-27
申请人： Masaru Kojima , Toshio Yamada
发明人： Masaru Kojima , Toshio Yamada
IPC分类号： B01D45/08 , B01D45/12 , B04C3/00 , F01N3/08 , F01N3/20 , F01N3/28 , F15D1/02 , F16L55/24 , F02C7/052
CPC分类号： B01D45/08 , B01D45/12 , F01N3/0892 , F01N3/2013 , F01N3/28 , F01N3/2892 , F16L55/24 , Y02T10/26
摘要： A gas flow pass has a gas flow direction deflecting member arranged in the gas flow pass for deflecting a gas flow direction outward with respect to a center of the gas flow pass, and a foreign substance trapping member arranged at a downstream position of the gas flow direction deflecting member and arranged on a part of or all of an inner surface of the gas flow pass. Therefore, it is possible to obtain the gas flow pass which can prevent a damage of the foreign substances in the gas flow and have a long term reliability.
摘要翻译：气体流路具有设置在气体流路中的气体流动方向偏转构件，用于相对于气体流路的中心向外偏转气体流动方向，并且布置在气体流动的下游位置处的异物捕获构件方向偏转构件并且布置在气体流动通道的内表面的一部分或全部上。因此，可以获得能够防止气体流中的异物的损伤而具有长期可靠性的气体流路。

50. 发明授权

US5274280A Semiconductor integrated circuit device having separate supply voltages for the logic stage and output stage 失效
标题翻译：具有用于逻辑级和输出级的单独电源电压的半导体集成电路器件
公开(公告)号：US5274280A
公开(公告)日：1993-12-28
申请号：US759428
申请日：1991-09-13
申请人： Yuko Ito , Toshio Yamada , Atsushi Shimizu , Kazuo Tanaka , Sukehiro Yoshida
发明人： Yuko Ito , Toshio Yamada , Atsushi Shimizu , Kazuo Tanaka , Sukehiro Yoshida
IPC分类号： H01L21/822 , H01L21/82 , H01L27/02 , H01L27/04 , H03K19/003 , H03K19/086 , H03K17/16
CPC分类号： H03K19/00353 , H03K19/086 , H01L27/0229
摘要： A semiconductor integrated circuit device has a plurality of emitter-coupled logic (ECL) gates. Separate power source wiring lines are provided for current switch circuits and emitter follower output circuits for the gates. The separate sets of power source wiring lines are respectively coupled to the corresponding external terminals of the semiconductor integrated circuit device. The power source wiring lines for each set are arranged adjacent one another on a semiconductor chip in order that they may be short circuited or kept separated depending upon the package structure of the semiconductor integrated circuit device.
摘要翻译：半导体集成电路器件具有多个发射极耦合逻辑（ECL）门。为电流开关电路和栅极的射极跟随器输出电路提供单独的电源布线。分开的电源布线组分别耦合到半导体集成电路器件的对应的外部端子。每组的电源布线在半导体芯片上彼此相邻布置，以便根据半导体集成电路器件的封装结构，它们可以短路或保持分离。

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