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41. 发明申请

US20060171224A1 1T-nmemory cell structure and its method of formation and operation 审中-公开
标题翻译： 1T核心细胞结构及其形成和操作方法
公开(公告)号：US20060171224A1
公开(公告)日：2006-08-03
申请号：US11394233
申请日：2006-03-31
申请人： Hasan Nejad , Mirmajid Seyyedy
发明人： Hasan Nejad , Mirmajid Seyyedy
IPC分类号： G11C7/00
CPC分类号： G11C11/16 , G11C5/02 , G11C11/22 , G11C13/0011 , G11C13/004 , G11C2013/0054 , G11C2213/71 , H01L27/228 , H01L27/24
摘要： A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.
摘要翻译：存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度列设置在相应的堆叠存储层中。

42. 发明申请

US20050226038A1 Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation 有权
标题翻译：堆叠柱状1T-nMTj MRAM结构及其形成和操作方法
公开(公告)号：US20050226038A1
公开(公告)日：2005-10-13
申请号：US11142448
申请日：2005-06-02
申请人： Hasan Nejad , Mirmajid Seyyedy
发明人： Hasan Nejad , Mirmajid Seyyedy
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： H01L27/228 , G11C5/02 , G11C11/16
摘要： This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.
摘要翻译：本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。通过使用单个存取晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数设置在相应的堆叠存储层中。

43. 发明授权

US06882553B2 Stacked columnar resistive memory structure and its method of formation and operation 有权
标题翻译：堆叠柱状电阻记忆结构及其形成和操作方法
公开(公告)号：US06882553B2
公开(公告)日：2005-04-19
申请号：US10214167
申请日：2002-08-08
申请人： Hasan Nejad , Mirmajid Seyyedy
发明人： Hasan Nejad , Mirmajid Seyyedy
IPC分类号： G11C11/00 , G11C11/16 , G11C7/00
CPC分类号： H01L27/228 , G11C5/02 , G11C11/16
摘要： This invention relates to a resistive memory array architecture which incorporates certain advantages from both cross-point and one transistor per cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the one transistor per cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of resistive memory cells each column being provided in a respective stacked memory layer.
摘要翻译：本发明涉及一种电阻存储器阵列架构，其结合了在读取操作期间每个单元结构的交叉点和一个晶体管的某些优点。通过使用单个存取晶体管来控制多个堆叠列的电阻存储器单元的读取，都利用了每个单元架构的一个晶体管的快速读取时间和更高的信噪比以及交叉点架构的较高的堆积密度每列设置在相应的堆叠存储层中。

44. 发明授权

US06780654B2 Methods of forming magnetoresistive memory device assemblies 有权
标题翻译：形成磁阻存储器件组件的方法
公开(公告)号：US06780654B2
公开(公告)日：2004-08-24
申请号：US10321165
申请日：2002-12-16
申请人： Hasan Nejad , James G. Deak
发明人： Hasan Nejad , James G. Deak
IPC分类号： H01L2100
CPC分类号： H01L27/222
摘要： The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.
摘要翻译：本发明包括在一对导线之间包括MRAM器件的结构。每个导线可以产生包围MRAM装置的至少一部分的磁场。每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。本发明还包括形成包含MRAM器件的组件的方法。在衬底上形成多个MRAM器件。导电材料形成在MRAM器件上，并被图案化成多条线。这些线与MRAM器件一一对应，并且彼此间隔开。在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。

45. 发明授权

US08426305B2 Method of fabricating integrated circuitry 有权
标题翻译：集成电路的制造方法
公开(公告)号：US08426305B2
公开(公告)日：2013-04-23
申请号：US13069005
申请日：2011-03-22
申请人： Hasan Nejad , James E. Green
发明人： Hasan Nejad , James E. Green
IPC分类号： H01L21/00
CPC分类号： H01L21/76838 , H01L21/76805 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.
摘要翻译：本发明包括制造集成电路的方法。在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。在互连通孔内提供互连导电金属。考虑了其他方面和实现。

46. 发明授权

US07989251B2 Variable resistance memory device having reduced bottom contact area and method of forming the same 有权
标题翻译：具有减小的底部接触面积的可变电阻存储器件及其形成方法
公开(公告)号：US07989251B2
公开(公告)日：2011-08-02
申请号：US11798459
申请日：2007-05-14
申请人： Hasan Nejad
发明人： Hasan Nejad
IPC分类号： H01L21/00
CPC分类号： H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16
摘要： A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.
摘要翻译：一种可变电阻记忆元件及其形成方法。存储元件包括支撑具有小的底部接触区域的底部电极的衬底。在底部电极上形成可变电阻材料，使得可变电阻材料具有与底部电极电连通的表面，并且顶部电极形成在可变电阻材料上。小的底部电极接触面积减小了复位电流要求，进而降低了每个位的写入晶体管尺寸。

47. 发明申请

US20110171825A1 Method of Fabricating Integrated Circuitry 有权
标题翻译：制作集成电路的方法
公开(公告)号：US20110171825A1
公开(公告)日：2011-07-14
申请号：US13069005
申请日：2011-03-22
申请人： Hasan Nejad , James E. Green
发明人： Hasan Nejad , James E. Green
IPC分类号： H01L21/768
CPC分类号： H01L21/76838 , H01L21/76805 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.
摘要翻译：本发明包括制造集成电路的方法。在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。在互连通孔内提供互连导电金属。考虑了其他方面和实现。

48. 发明申请

US20080227289A1 Method of Fabricating Integrated Circuitry 有权
标题翻译：制作集成电路的方法
公开(公告)号：US20080227289A1
公开(公告)日：2008-09-18
申请号：US12121258
申请日：2008-05-15
申请人： Hasan Nejad , James E. Green
发明人： Hasan Nejad , James E. Green
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76805 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.
摘要翻译：本发明包括制造集成电路的方法。在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。在互连通孔内提供互连导电金属。考虑了其他方面和实现。

49. 发明授权

US07279762B2 Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies 有权
标题翻译：磁阻存储器件组件，以及形成磁阻存储器件组件的方法
公开(公告)号：US07279762B2
公开(公告)日：2007-10-09
申请号：US11295177
申请日：2005-12-05
申请人： Hasan Nejad , James G. Deak
发明人： Hasan Nejad , James G. Deak
IPC分类号： H01L29/82
CPC分类号： H01L27/222
摘要： The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.
摘要翻译：本发明包括在一对导线之间包括MRAM器件的结构。每个导线可以产生包围MRAM装置的至少一部分的磁场。每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。本发明还包括形成包含MRAM器件的组件的方法。在衬底上形成多个MRAM器件。导电材料形成在MRAM器件上，并被图案化成多条线。这些线与MRAM器件一一对应，并且彼此间隔开。在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。

50. 发明申请

US20060076635A1 Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies 有权
标题翻译：磁阻存储器件组件，以及形成磁阻存储器件组件的方法
公开(公告)号：US20060076635A1
公开(公告)日：2006-04-13
申请号：US11295177
申请日：2005-12-05
申请人： Hasan Nejad , James Deak
发明人： Hasan Nejad , James Deak
IPC分类号： H01L43/00
CPC分类号： H01L27/222
摘要： The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.
摘要翻译：本发明包括在一对导线之间包括MRAM器件的结构。每个导线可以产生包围MRAM装置的至少一部分的磁场。每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。本发明还包括形成包含MRAM器件的组件的方法。在衬底上形成多个MRAM器件。导电材料形成在MRAM器件上，并被图案化成多条线。这些线与MRAM器件一一对应，并且彼此间隔开。在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。

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