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41. 发明申请

US20120187420A1 STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL 有权
标题翻译：结构和方法替代金属门和接触金属
公开(公告)号：US20120187420A1
公开(公告)日：2012-07-26
申请号：US13427963
申请日：2012-03-23
申请人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
发明人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
IPC分类号： H01L29/16 , H01L29/78
CPC分类号： H01L23/485 , H01L21/28088 , H01L21/28202 , H01L21/76283 , H01L21/76877 , H01L21/823842 , H01L21/823871 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.
摘要翻译：提供了一种电气装置，其在一个实施例中包括具有第一栅极结构的p型半导体器件，该第一栅极结构包括存在于半导体衬底上的栅极电介质，p型功函数金属层，由钛构成的金属层和铝和由铝构成的金属填充物。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。层间电介质存在于半导体衬底上。层间电介质包括到p型和n型半导体器件的源区和漏区的互连。互连由钛和铝构成的金属层和由铝组成的金属填充物构成。本公开还提供了形成上述结构的方法。

42. 发明申请

US20120119302A1 Trench Silicide Contact With Low Interface Resistance 审中-公开
标题翻译：沟槽硅化物接触低接口电阻
公开(公告)号：US20120119302A1
公开(公告)日：2012-05-17
申请号：US12944018
申请日：2010-11-11
申请人： Chengwen Pei , Jeffrey B. Johnson , Zhengwen Li , Jian Yu
发明人： Chengwen Pei , Jeffrey B. Johnson , Zhengwen Li , Jian Yu
IPC分类号： H01L23/532 , H01L21/28 , H01L29/78
CPC分类号： H01L21/76879 , H01L21/26586 , H01L21/28518 , H01L21/76805 , H01L23/485 , H01L29/41766 , H01L29/517 , H01L29/66545 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.
摘要翻译：提供一种电结构，其包括存在于半导体衬底上的电介质层和通过电介质层存在的通路开口。在通孔开口内存在互连。在半导体衬底中存在金属半导体合金接触。金属半导体合金触点具有由相对于通孔开口的中心线的凸曲面限定的周长。限定金属半导体合金触点的凸曲率的端点与通孔开口的侧壁，互连的侧壁和半导体衬底的上表面之间的界面对准。

43. 发明授权

US09006801B2 Method for forming metal semiconductor alloys in contact holes and trenches 有权
标题翻译：在接触孔和沟槽中形成金属半导体合金的方法
公开(公告)号：US09006801B2
公开(公告)日：2015-04-14
申请号：US13013081
申请日：2011-01-25
申请人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
发明人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
IPC分类号： H01L21/285 , H01L21/336 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/311 , H01L21/768
CPC分类号： H01L29/7833 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/28518 , H01L21/31116 , H01L21/32053 , H01L21/321 , H01L21/32133 , H01L21/76802 , H01L21/76805 , H01L21/76829 , H01L23/535 , H01L29/1054 , H01L29/45 , H01L29/456 , H01L29/458 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7843 , H01L29/7845 , H01L29/7849
摘要： A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.
摘要翻译：提供一种形成半导体器件的方法，包括在半导体容纳表面上形成第一金属半导体合金，在第一金属半导体合金上形成电介质层，在电介质层中形成开口以提供第一金属半导体合金，并且在第一金属半导体合金的暴露表面上形成第二金属半导体合金。在另一个实施例中，该方法包括在半导体衬底的沟道区上形成栅极结构，在至少源极区和漏极区上形成电介质层，在电介质层中形成开口以提供暴露表面，半导体衬底在所述半导体衬底的暴露表面上形成第一金属半导体合金，并在所述第一金属半导体合金上形成第二金属半导体合金。

44. 发明授权

US08673737B2 Array and moat isolation structures and method of manufacture 有权
标题翻译：阵列和护城隔离结构及其制造方法
公开(公告)号：US08673737B2
公开(公告)日：2014-03-18
申请号：US13274389
申请日：2011-10-17
申请人： Naoyoshi Kusaba , Oh-jung Kwon , Zhengwen Li , Hongwen Yan
发明人： Naoyoshi Kusaba , Oh-jung Kwon , Zhengwen Li , Hongwen Yan
IPC分类号： H01L21/76
CPC分类号： H01L29/423 , H01L21/762 , H01L27/10805 , H01L27/10829 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.
摘要翻译：提供了一种用于eDRAM的阵列或护城隔离结构及其制造方法。该方法包括形成用于存储器阵列的深沟槽和隔离区域。该方法包括在用于存储器阵列和隔离区域的深沟槽的暴露表面上形成节点电介质。该方法包括用金属填充用于存储器阵列的深沟槽的剩余部分，并用金属衬里隔离区域的深沟槽。该方法包括用用于存储器阵列的深沟槽内的金属上的材料填充用于隔离区域的深沟槽的剩余部分。该方法包括使用于存储器阵列和隔离区域的深沟槽内的金属凹陷。存储器阵列的深沟槽中的金属凹陷到比隔离区域中的金属更深的深度。

45. 发明授权

US08476530B2 Self-aligned nano-scale device with parallel plate electrodes 失效
标题翻译：具有平行平板电极的自对准纳米级装置
公开(公告)号：US08476530B2
公开(公告)日：2013-07-02
申请号：US12488948
申请日：2009-06-22
申请人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
IPC分类号： H01B5/14
CPC分类号： B81C1/00698 , B81B2201/0292
摘要： A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
摘要翻译：连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。形成间隙填充层以堵塞第一沟槽部分中的空间。将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

46. 发明申请

US20120326125A1 Deposition On A Nanowire Using Atomic Layer Deposition 有权
标题翻译：使用原子层沉积在纳米线上沉积
公开(公告)号：US20120326125A1
公开(公告)日：2012-12-27
申请号：US13604739
申请日：2012-09-06
申请人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang , Yu Zhu
发明人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang , Yu Zhu
IPC分类号： H01L29/775 , H01L21/30 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/42392 , H01L29/47 , H01L29/6675 , H01L29/7839 , H01L51/0048 , H01L51/0516 , H01L51/0558 , H01L51/057 , Y10S977/762 , Y10S977/938
摘要： A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.
摘要翻译：半导体器件包括衬底，纳米线，第一结构和第二结构。纳米线悬挂在第一结构和第二结构之间，其中第一结构和第二结构超过衬底，其中纳米线包括纳米线表面上的层，其中该层包括硅化物和碳化物中的至少一种，其中该层具有基本均匀的形状。

47. 发明申请

US20120187375A1 Deposition On A Nanowire Using Atomic Layer Deposition 有权
标题翻译：使用原子层沉积在纳米线上沉积
公开(公告)号：US20120187375A1
公开(公告)日：2012-07-26
申请号：US13013067
申请日：2011-01-25
申请人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang , Yu Zhu
发明人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang , Yu Zhu
IPC分类号： H01L29/775 , H01L21/335 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/42392 , H01L29/47 , H01L29/6675 , H01L29/7839 , H01L51/0048 , H01L51/0516 , H01L51/0558 , H01L51/057 , Y10S977/762 , Y10S977/938
摘要： In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire.
摘要翻译：在一个示例性实施例中，一种方法包括：提供具有衬底，纳米线，第一结构和第二结构的半导体器件，其中纳米线悬挂在第一结构和第二结构之间，其中第一结构和第二结构过度的底物; 以及进行原子层沉积以在所述半导体器件的至少一部分上沉积膜，其中进行原子层沉积以沉积所述膜包括进行原子层沉积以将所述膜沉积在所述纳米线的至少一个表面上。

48. 发明申请

US20120104469A1 REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE 有权
标题翻译：具有高性能门电极的替代栅极MOSFET
公开(公告)号：US20120104469A1
公开(公告)日：2012-05-03
申请号：US12912963
申请日：2010-10-27
申请人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
发明人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42368 , H01L29/42376 , H01L29/49 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/78 , H01L29/7833
摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.
摘要翻译：在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。栅组件可以用作栅极电介质或功函数金属部分，以形成增强替代栅极场效应晶体管的性能的栅极结构。

49. 发明申请

US20120061234A1 Deposition Chamber Cleaning Method Including Stressed Cleaning Layer 有权
标题翻译：沉积室清洁方法包括压实清洁层
公开(公告)号：US20120061234A1
公开(公告)日：2012-03-15
申请号：US12878128
申请日：2010-09-09
申请人： Tien-Jen Cheng , Zhengwen Li , Keith Kwong Hon Wong
发明人： Tien-Jen Cheng , Zhengwen Li , Keith Kwong Hon Wong
IPC分类号： B08B7/04 , C23C14/34 , C23C16/00
CPC分类号： B08B7/04 , B08B7/0014 , C23C14/34 , C23C16/4404
摘要： A method for cleaning a deposition chamber includes forming a deposited layer over an interior surface of the deposition chamber, wherein the deposited layer has a deposited layer stress and a deposited layer modulus; forming a cleaning layer over the deposited layer, wherein a material comprising the cleaning layer is selected such that the cleaning layer adheres to the deposited layer, and has a cleaning layer stress and a cleaning layer modulus, wherein the cleaning layer stress is higher than the deposited layer stress, and wherein the cleaning layer modulus is higher than the deposited layer modulus; and removing the deposited layer and the cleaning layer from the interior of the deposition chamber.
摘要翻译：清理沉积室的方法包括在沉积室的内表面上形成沉积层，其中沉积层具有沉积层应力和沉积层模量; 在所述沉积层上形成清洁层，其中选择包括所述清洁层的材料，使得所述清洁层粘附到所述沉积层，并且具有清洁层应力和清洁层模量，其中所述清洁层应力高于沉积层应力，并且其中所述清洁层模量高于所述沉积层模量; 以及从沉积室的内部去除沉积层和清洁层。

50. 发明申请

US20110316343A1 PHOTOVOLTAIC MODULE WITH INTEGRATED DIAGNOSTICS 审中-公开
标题翻译：具有综合诊断的光伏模块
公开(公告)号：US20110316343A1
公开(公告)日：2011-12-29
申请号：US13154037
申请日：2011-06-06
申请人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
发明人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
IPC分类号： H02J1/00
CPC分类号： H01L31/02021 , Y02E10/50 , Y10T307/685
摘要： A photovoltaic module (10) comprises a plurality of solar cells (20) interconnected in serial arrays (15). At least some of the solar cells (20) are equipped with control units (30) comprising at least one thermal sensor (42) and one power sensor (43). The control unit (30) comprises means (35) for removing a specific solar cell (20′) from the photovoltaic module (10) network if said solar cell (20′) is found to have reached a predefined level of degradation. In a preferred embodiment, control unit (30) is an ASIC chip (40) in thermal contact with said solar cell (20) and electrically connected to said solar cell (20).
摘要翻译：光伏模块（10）包括以串联阵列（15）互连的多个太阳能电池（20）。至少一些太阳能电池（20）装备有包括至少一个热传感器（42）和一个功率传感器（43）的控制单元（30）。如果发现所述太阳能电池（20'）达到预定水平的降级，则控制单元（30）包括用于从光伏模块（10）网络去除特定太阳能电池（20'）的装置（35）。在优选实施例中，控制单元（30）是与所述太阳能电池（20）热接触并电连接到所述太阳能电池（20）的ASIC芯片（40）。

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