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41. 发明授权

US07671362B2 Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing 失效
标题翻译：用于确定双镶嵌加工的最佳种子和衬层层厚度的测试结构
公开(公告)号：US07671362B2
公开(公告)日：2010-03-02
申请号：US11953568
申请日：2007-12-10
申请人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
发明人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
IPC分类号： H01L23/58
CPC分类号： H01L22/12 , H01L22/34
摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.
摘要翻译：集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化，相同的沉积工艺条件。

42. 发明申请

US20090294901A1 STRUCTURE AND METHOD OF FORMING ELECTRICALLY BLOWN METAL FUSES FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路形成电动金属熔断器的结构与方法
公开(公告)号：US20090294901A1
公开(公告)日：2009-12-03
申请号：US12132337
申请日：2008-06-03
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Jeffrey P. Gambino , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Jeffrey P. Gambino , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
IPC分类号： H01L21/768 , H01L23/58
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.
摘要翻译：用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。

43. 发明申请

US20080231312A1 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US20080231312A1
公开(公告)日：2008-09-25
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

44. 发明授权

US06870263B1 Device interconnection 失效
标题翻译：设备互连
公开(公告)号：US06870263B1
公开(公告)日：2005-03-22
申请号：US09052688
申请日：1998-03-31
申请人： Lawrence A. Clevenger , Ronald G. Filippi , Mark Hoinkis , Jeffery L. Hurd , Roy C. Iggulden , Herbert Palm , Hans W. Poetzlberger , Kenneth P. Rodbell , Florian Schnabel , Stefan Weber , Ebrahim A. Mehter
发明人： Lawrence A. Clevenger , Ronald G. Filippi , Mark Hoinkis , Jeffery L. Hurd , Roy C. Iggulden , Herbert Palm , Hans W. Poetzlberger , Kenneth P. Rodbell , Florian Schnabel , Stefan Weber , Ebrahim A. Mehter
IPC分类号： H01L21/28 , H01L21/768 , H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76849 , H01L21/76876 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.
摘要翻译：用于互连具有改进的可靠性的集成电路部件的导体。导体包括围绕导体的至少三个表面的衬垫，产生低纹理导体。已经发现，低纹理导体导致改善的电迁移寿命。

45. 发明授权

US06518670B1 Electrically porous on-chip decoupling/shielding layer 有权
标题翻译：多孔片上去耦/屏蔽层
公开(公告)号：US06518670B1
公开(公告)日：2003-02-11
申请号：US10091643
申请日：2002-03-06
申请人： Jack A. Mandelman , Ronald G. Filippi , Jeffrey P. Gambino , Richard A. Wachnik
发明人： Jack A. Mandelman , Ronald G. Filippi , Jeffrey P. Gambino , Richard A. Wachnik
IPC分类号： H01L2940
CPC分类号： H01L21/76897 , H01L23/5222 , H01L23/5228 , H01L23/5286 , H01L27/0802 , H01L27/0805 , H01L28/82 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes interconnected conductor lines comprising a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines are formed on the top surface of the lower ILD layer surrounded by an insulator formed on the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and it is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on a upper level. Each has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer is formed below the intermediate conductor to electrically insulate and separate the intermediate conductor lines from the lower conductor lines. A upper ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines. The resistive stud, the capacitor dielectric, and the intermediate conductor across the capacitor dielectric layer and the liner layer form an electrically porous, distributed resistive-capacitive low-pass decoupling network.
摘要翻译：半导体器件包括互连的导体线，其包括在衬底上形成有顶表面的下层间介电层（ILD）层。在由形成在下ILD层上的绝缘体围绕的下ILD层的顶表面上形成几个下导体线。一组电阻螺柱中的每一个具有侧壁，下端和上端，并且在下端处连接到下导体线的顶部。在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。上导体线形成在上层。每个具有与相应的一个电阻螺柱接触的底表面。在中间导体下方形成中心ILD层，以将中间导线与下导体线电绝缘和分离。上部ILD层覆盖中间导体，用于将中间导体线与上部导体线电绝缘和分离。电阻螺柱，电容器电介质和跨过电容器电介质层和衬层的中间导体形成电多孔分布式电阻电容低通去耦网络。

46. 发明授权

US08962467B2 Metal fuse structure for improved programming capability 有权
标题翻译：金属保险丝结构，提高编程能力
公开(公告)号：US08962467B2
公开(公告)日：2015-02-24
申请号：US13399266
申请日：2012-02-17
申请人： Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon , Junjing Bao
发明人： Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Ronald G. Filippi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon , Junjing Bao
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01H69/02 , H01H85/046 , H01H2085/0275 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.
摘要翻译：提供更可靠的保险丝熔断位置的结构及其制作方法。在熔断器熔断之前，垂直金属保险丝熔断结构在熔丝导体有意损坏的部分。损坏的部分有助于熔断器在已知位置中熔断，从而降低后吹回路中的电阻变化。同时，在保险丝熔断之前，保险丝结构能够正常工作。熔丝导体的损坏部分是通过在保险丝导体的一部分上方的盖层中形成开口，并蚀刻熔丝导体而制成的。优选地，开口对准，使得损坏部分在熔丝导体的顶角上。可以在与损坏的保险丝导体相邻的绝缘体中形成空腔。具有空腔的损坏的保险丝结构可以容易地结合在制造具有气隙的集成电路的过程中。

47. 发明申请

US20130234284A1 Fuse and Integrated Conductor 有权
标题翻译：保险丝和集成导体
公开(公告)号：US20130234284A1
公开(公告)日：2013-09-12
申请号：US13414742
申请日：2012-03-08
申请人： Griselda Bonilla , Kaushik Chanda , Samuel Sung Shik Choi , Ronald G. Filippi , Stephan Grunow , Naftali Eliahu Lustig , Andrew H. Simon
发明人： Griselda Bonilla , Kaushik Chanda , Samuel Sung Shik Choi , Ronald G. Filippi , Stephan Grunow , Naftali Eliahu Lustig , Andrew H. Simon
IPC分类号： H01L23/525 , H01L21/02
CPC分类号： H01L23/5256 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.
摘要翻译：熔丝结构包括在位于衬底之上的电介质层内的孔内，孔暴露在衬底内的导体接触层，介于导体接触层和另一导体层之间的晶种层。种子层包括掺杂的铜材料，其包括主要在种子层内固定的掺杂剂。可以切断熔丝结构，同时不切断也位于衬底上的导体互连结构，所述导体互连结构在第二孔内暴露第二导体接触层。与包括具有固定化掺杂剂的掺杂种子层的熔丝结构相反，互连结构包括具有可移动掺杂剂的掺杂种子层。

48. 发明授权

US07776737B2 Reliability of wide interconnects 失效
标题翻译：宽互连的可靠性
公开(公告)号：US07776737B2
公开(公告)日：2010-08-17
申请号：US12191534
申请日：2008-08-14
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert
IPC分类号： H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76816 , H01L21/76805 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.
摘要翻译：一种集成电路，其包括半导体衬底，所述半导体衬底上的包括金属布线的第一金属布线级别，所述第一金属布线层上的互连布线级别，其包括层间电介质内的通孔布线，第二金属布线级别包括金属布线的互连布线层，至少一个具有多个介电填充形状的金属布线，其减小了所述至少一个金属布线的横截面积，并且其中所述通孔互连使金属线在第一布线级别和第二布线级中的至少一个金属布线中，通孔布线与多个介质填充形状相邻并间隔开。还公开了一种方法，其中多个介电填充形状被放置成与第二布线层中的布线中的通孔接触区域相邻并间隔开。

49. 发明授权

US07397260B2 Structure and method for monitoring stress-induced degradation of conductive interconnects 有权
标题翻译：用于监测导电互连的应力诱导退化的结构和方法
公开(公告)号：US07397260B2
公开(公告)日：2008-07-08
申请号：US11163948
申请日：2005-11-04
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

50. 发明授权

US09093164B2 Redundant via structure for metal fuse applications 有权
标题翻译：金属保险丝应用的冗余通孔结构
公开(公告)号：US09093164B2
公开(公告)日：2015-07-28
申请号：US13298661
申请日：2011-11-17
申请人： Ronald G. Filippi , Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon
发明人： Ronald G. Filippi , Griselda Bonilla , Kaushik Chanda , Samuel S. Choi , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon
IPC分类号： H01H85/04 , G11C17/16 , H01L23/525 , H01L23/522 , G11C29/00 , H01H85/46 , H01L23/532
CPC分类号： G11C17/16 , G11C29/702 , H01H2085/466 , H01L23/5226 , H01L23/5256 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A metal fuse structure using redundant vias formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes a first dielectric layer having a conductor, a second dielectric layer above the first dielectric layer having a first conductive line and a first via, the first via is on the conductor, the first conductive line is on the first via, the first via is the only electrical connection between the first conductive line and the conductor, and a third dielectric layer above the second dielectric layer having a second conductive line, a second via and a third via, the second via and the third via are both on the first conductive line, the second conductive line is on both the first via and the second via.
摘要翻译：一种金属熔断器结构，其使用在堆叠的通孔金属熔丝结构中的一个金属层上形成的冗余通孔，以迫使在不具有冗余通孔的金属层中发生故障。金属熔丝结构包括具有导体的第一电介质层，在第一电介质层之上的第二电介质层，具有第一导电线和第一通孔，第一通孔位于导体上，第一导电线在第一通孔上，所述第一通孔是所述第一导线与所述导体之间的唯一电连接，并且所述第二电介质层上方的第三电介质层具有第二导电线，第二通孔和第三通孔，所述第二通孔和所述第三通孔均为在第一导线上，第二导线在第一通孔和第二通孔上。

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