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41. 发明授权

US07504299B2 Folded node trench capacitor 有权
标题翻译：折叠节点沟槽电容器
公开(公告)号：US07504299B2
公开(公告)日：2009-03-17
申请号：US10597432
申请日：2004-01-30
申请人： Thomas W. Dyer , Carl Radens
发明人： Thomas W. Dyer , Carl Radens
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/87 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting the one or more ground plate to the substrate; the charge storage plates are connected at the top of the capacitor by blocking the end of the first plate during the formation of the second ground plate and exposing the material of the first storage plate during deposition of the second storage plate.
摘要翻译：通过连续沉积电介质和导体层并且通过将穿过板的孔蚀刻到衬底中的掩埋板并且连接一个或多个接地而与接地板接触而将沟槽电容器填充一组两个或更多个存储板板到基板; 电荷存储板通过在形成第二接地板期间阻挡第一板的端部并且在第二存储板的沉积期间暴露第一存储板的材料而在电容器的顶部连接。

42. 发明申请

US20090039442A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090039442A1
公开(公告)日：2009-02-12
申请号：US11834398
申请日：2007-08-06
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

43. 发明授权

US07488660B2 Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure 有权
标题翻译：用于增强接触面积的扩展的源极/漏极结构和用于形成延伸的升高的源极/漏极结构的方法
公开(公告)号：US07488660B2
公开(公告)日：2009-02-10
申请号：US11307759
申请日：2006-02-21
申请人： Thomas W. Dyer , Sunfei Fang
发明人： Thomas W. Dyer , Sunfei Fang
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/823418 , H01L21/823425 , H01L21/823475 , H01L21/823871 , H01L29/517 , H01L29/66628 , H01L29/7834
摘要： A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 Å to about 200 Å are formed with a vertical leg on the sidewalls of the stack and a horizontal leg reaching over the LDD/LDS regions next to the stack. RSD regions are formed in contact with the substrate aside from the etch-stop layers. The RSD regions cover the horizontal leg of the etch-stop layer and cover at least a portion of the vertical leg of the etch-stop layer on the sidewall of the gate electrode.
摘要翻译：半导体器件包括具有侧壁的栅极电极堆叠和具有栅极电介质层和栅电极的顶表面，并且衬底中的LDD / LDS区域与堆叠对准。形成厚度为约至约200的保形L形蚀刻停止层，其在堆叠的侧壁上具有垂直支腿，并且在堆叠旁边的LDD / LDS区域上形成水平支线。除了蚀刻停止层之外，RSD区域与基板形成接触。 RSD区域覆盖蚀刻停止层的水平支腿并且覆盖栅电极的侧壁上的蚀刻停止层的垂直支腿的至少一部分。

44. 发明授权

US07488659B2 Structure and methods for stress concentrating spacer 失效
标题翻译：应力集中垫片的结构和方法
公开(公告)号：US07488659B2
公开(公告)日：2009-02-10
申请号：US11692371
申请日：2007-03-28
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843 , Y10S438/938
摘要： A stress-concentrating spacer structure is a stack of an upper gate spacer with a low Young's modulus and a lower gate spacer with a high Young's modulus. The stacked spacer structure surrounds the gate electrode. The stress-concentrating spacer structure may contact an inner gate spacer that contacts the gate electrode or may directly contact the gate electrode. The upper gate spacer deforms substantially more than the lower gate spacer. The stress generated by the stress liner is thus transmitted primarily through the lower gate spacer to the gate electrode and subsequently to the channel of the MOSFET. The efficiency of the transmission of the stress from the stress liner to the channel is thus enhanced compared to conventional MOSFETs structure with a vertically uniform composition within a spacer.
摘要翻译：应力集中的间隔结构是具有低杨氏模量的上栅极间隔物和具有高杨氏模量的下栅极间隔物的堆叠。层叠的间隔结构围绕栅电极。应力集中的间隔物结构可以接触与栅电极接触的内部栅极间隔物，或者可以直接接触栅电极。上栅极间隔件基本上比下栅极间隔件更大地变形。因此，应力衬垫产生的应力主要通过下栅极隔离物传输到栅电极，随后传输到MOSFET的沟道。因此与在间隔物内具有垂直均匀组成的常规MOSFET结构相比，应力衬底向通道传递应力的效率得到提高。

45. 发明授权

US07485516B2 Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation 失效
标题翻译：在氧化之前将氮离子注入到半导体衬底中用于偏移间隔物形成的方法
公开(公告)号：US07485516B2
公开(公告)日：2009-02-03
申请号：US11164376
申请日：2005-11-21
申请人： Thomas W. Dyer , Jinhong Li , Zhijiong Luo
发明人： Thomas W. Dyer , Jinhong Li , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28247
摘要： A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.
摘要翻译：形成集成电路器件的方法包括在半导体的一部分上形成栅电极堆叠。堆叠包括其上方具有栅电极的栅介质层。将双原子氮和/或氮原子从堆叠中以最低能量小于或等于10keV的双原子氮并且在小于或等于5keV的最大能量下，在低于或等于等于1000℃，时间小于或等于30分钟。然后在堆叠的侧壁上形成氧化硅偏移间隔物。在偏移间隔物之外的衬底中形成源极/漏极延伸区域。在氮注入层的另一部分上的偏移间隔物的外表面上形成氮化物侧壁间隔物。然后在侧壁间隔物之外形成衬底中的源极/漏极区域。

46. 发明申请

US20090017625A1 Methods For Removing Gate Sidewall Spacers In CMOS Semiconductor Fabrication Processes 有权
标题翻译： CMOS半导体制造工艺中去除栅极侧壁间隔物的方法
公开(公告)号：US20090017625A1
公开(公告)日：2009-01-15
申请号：US11778038
申请日：2007-07-14
申请人： Kyoung Woo Lee , Ja Hum Ku , JunJung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , JunJung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
摘要翻译：提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制或以其它方式阻碍或限制后续工艺流程。

47. 发明授权

US07456450B2 CMOS devices with hybrid channel orientations and method for fabricating the same 有权
标题翻译：具有混合信道取向的CMOS器件及其制造方法
公开(公告)号：US07456450B2
公开(公告)日：2008-11-25
申请号：US11307481
申请日：2006-02-09
申请人： Thomas W. Dyer , Xiangdong Chen , James J. Toomey , Haining S. Yang
发明人： Thomas W. Dyer , Xiangdong Chen , James J. Toomey , Haining S. Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/82385 , H01L21/823857
摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.
摘要翻译：本发明涉及包括至少第一和第二器件区域的半导体衬底，其中第一器件区域包括具有沿着第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件区域包括第二凹部，沿着第二不同组的等效晶面取向的内表面。可以使用这种半导体衬底形成半导体器件结构。具体而言，可以在第一器件区域形成至少一个n沟道场效应晶体管（n-FET），该第一器件区域包括沿着第一凹槽的内表面延伸的沟道。至少一个p沟道场效应晶体管（p-FET）可以在第二器件区域形成，该第二器件区域包括沿着第二凹槽的内表面延伸的沟道。

48. 发明申请

US20080246056A1 SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET 审中-公开
标题翻译：使用间隔层叠层的硅化物形成和硅氧烷沟道界面及相关PFET
公开(公告)号：US20080246056A1
公开(公告)日：2008-10-09
申请号：US11697806
申请日：2007-04-09
申请人： Victor W. C. Chan , Thomas W. Dyer , Sunfei Fang , Jinghong Li , Teck J. Tang , Henry K. Utomo , Jiang Yan
发明人： Victor W. C. Chan , Thomas W. Dyer , Sunfei Fang , Jinghong Li , Teck J. Tang , Henry K. Utomo , Jiang Yan
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823864 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7843
摘要： Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.
摘要翻译：在嵌入式硅锗（eSiGe）源极/漏极区域中使用与eSiGe和硅沟道之间的界面重叠的防止硅化物的衬垫形成硅化物的方法以及具有eSiGe源极/漏极区域和压应力衬垫的相关PFET 公开了其接近硅通道的方式。在一个实施例中，一种方法包括提供具有与其相邻的含氮隔离物的栅极和与栅极的硅沟道相邻的外延生长的硅锗（eSiGe）区域; 去除不在eSiGe源极/漏极区域和硅沟道之间的界面上延伸的含氮隔离物; 在栅极周围形成单个硅化物防止间隔物，单个硅化物防止间隔物与界面重叠; 以及使用单个硅化物防止间隔物在eSiGe源极/漏极区域中形成硅化物，以防止硅化物在硅沟道的至少延伸区域中形成。

49. 发明授权

US07390745B2 Pattern enhancement by crystallographic etching 有权
标题翻译：通过晶体蚀刻的图案增强
公开(公告)号：US07390745B2
公开(公告)日：2008-06-24
申请号：US11162800
申请日：2005-09-23
申请人： Thomas W. Dyer , Kenneth T. Settlemyer, Jr. , James J. Toomey , Haining Yang
发明人： Thomas W. Dyer , Kenneth T. Settlemyer, Jr. , James J. Toomey , Haining Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/30608 , H01L21/32134
摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
摘要翻译：与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。由于使用了常规处理，所以图案具有圆角的固有限制。使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

50. 发明申请

US20080048297A1 EMBEDDED INTERCONNECTS, AND METHODS FOR FORMING SAME 有权
标题翻译：嵌入式互连及其形成方法
公开(公告)号：US20080048297A1
公开(公告)日：2008-02-28
申请号：US11467712
申请日：2006-08-28
申请人： Haining Yang , Thomas W. Dyer
发明人： Haining Yang , Thomas W. Dyer
IPC分类号： H01L27/082
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.
摘要翻译：本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构并且将第一有源器件区域与第二有源器件区域连接。半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。

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