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41. 发明授权

US07400537B2 Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells 有权
标题翻译：用于使用单独验证擦除非易失性存储器的系统以及对存储器单元子集的额外擦除
公开(公告)号：US07400537B2
公开(公告)日：2008-07-15
申请号：US11296028
申请日：2005-12-06
申请人： Gerrit Jan Hemink , Teruhiko Kamei
发明人： Gerrit Jan Hemink , Teruhiko Kamei
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.
摘要翻译：一组非易失性存储元件被划分成用于擦除的子集，以避免擦除存储元件的擦除更快。整个元素组被擦除，直到该组元素的第一个子集被验证为被擦除为止。第一个子集可以包括更快的擦除单元。验证第一个子集包括从验证中排除第二个子集。在第一子集被验证为擦除之后，它们被禁止擦除，而第二子集被进一步擦除。当第二个子集被验证为擦除时，该组元素被验证为被擦除。验证该组元素被擦除可以包括排除第一子集验证或验证第一和第二子集在一起。使用不同的步长，这取决于要擦除和验证哪个子集，以便更有效和准确地擦除该组元素。

42. 发明申请

US20080158997A1 Systems For Erasing Non-Volatile Memory Using Individual Verification And Additional Erasing of Subsets of Memory Cells 有权
标题翻译：用于使用单独验证擦除非易失性存储器的系统以及对存储器单元子集的附加擦除
公开(公告)号：US20080158997A1
公开(公告)日：2008-07-03
申请号：US12040632
申请日：2008-02-29
申请人： Gerrit Jan Hemink , Teruhiko Kamei
发明人： Gerrit Jan Hemink , Teruhiko Kamei
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.
摘要翻译：一组非易失性存储元件被划分成用于擦除的子集，以避免擦除存储元件的擦除更快。整个元素组被擦除，直到该组元素的第一个子集被验证为被擦除为止。第一个子集可以包括更快的擦除单元。验证第一个子集包括从验证中排除第二个子集。在第一子集被验证为擦除之后，它们被禁止擦除，而第二子集被进一步擦除。当第二个子集被验证为擦除时，该组元素被验证为被擦除。验证该组元素被擦除可以包括排除第一子集验证或验证第一和第二子集在一起。使用不同的步长，这取决于要擦除和验证哪个子集，以便更有效和准确地擦除该组元素。

43. 发明申请

US20080002468A1 Partial Page Fail Bit Detection in Flash Memory Devices 有权
标题翻译：闪存设备中部分页面失败位检测
公开(公告)号：US20080002468A1
公开(公告)日：2008-01-03
申请号：US11428111
申请日：2006-06-30
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/349 , G06F11/1068 , G11C16/10
摘要： A flash memory device, and a method of operating the same, is disclosed. The array of the flash memory device is arranged in pages of memory cells, each page having memory cells associated into groups of memory cells within the page for purposes of fail bit detection in program verification. For example, these groups may correspond to sectors within the page. In a programming operation, the verify process determines whether each group of memory cells within the page has fewer than a selected ignore bit limit for the sector. If not, additional programming is required for the insufficiently programmed cells in the page. By applying a fail bit detection threshold for each of multiple groups within the page, the efficiency of error correction coding in the flash memory is improved. A similar verify and fail bit detection approach may be used in erase and soft programming operations.
摘要翻译：公开了一种闪速存储器件及其操作方法。闪存设备的阵列被布置在存储器单元的页面中，每个页面具有与页面内的存储器单元组相关联的存储器单元，用于程序验证中的故障位检测。例如，这些组可以对应于页面内的扇区。在编程操作中，验证过程确定页面内的每组存储器单元是否少于扇区的选定的忽略位限制。如果没有，页面中编程不足的单元格需要额外的编程。通过对页内的多个组中的每一个应用故障比特检测阈值，提高了闪速存储器中纠错编码的效率。类似的验证和故障位检测方法可用于擦除和软编程操作。

44. 发明申请

US20070297247A1 METHOD FOR PROGRAMMING NON-VOLATILE MEMORY USING VARIABLE AMPLITUDE PROGRAMMING PULSES 审中-公开
标题翻译：使用可变扩展编程脉冲编程非易失性存储器的方法
公开(公告)号：US20070297247A1
公开(公告)日：2007-12-27
申请号：US11426475
申请日：2006-06-26
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/04 , G11C7/00 , G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Non-volatile storage elements are programmed using a series of voltage waveforms, where each waveform includes different portions with different amplitudes. For example, the amplitudes can vary as a decreasing staircase or ramp. Storage elements which are to be programmed to the highest level are programmed using the entire waveform, while storage elements which are to be programmed to intermediate and lower levels are programmed using different portions of the waveform. For example, the storage elements to be programmed to the intermediate level are programmed using the last two-thirds of each waveform, while the storage elements to be programmed to the lower level are programmed using the last one-third of each waveform. For these storage elements, programming is inhibited for a portion of the waveform by applying an inhibit voltage to an associated bit line. Higher programming speeds and narrower threshold voltage distributions can be achieved.
摘要翻译：使用一系列电压波形编程非易失性存储元件，其中每个波形包括具有不同幅度的不同部分。例如，幅度可以随着降低的阶梯或斜坡而变化。要编程到最高级别的存储元件使用整个波形进行编程，而要编程到中间级和低级级的存储元件使用波形的不同部分进行编程。例如，要使用每个波形的最后三分之二对要编程到中间电平的存储元件进行编程，而要编程到较低电平的存储元件使用每个波形的最后三分之一进行编程。对于这些存储元件，通过向相关联的位线施加禁止电压来禁止一部分波形的编程。可以实现更高的编程速度和更窄的阈值电压分布。

45. 发明授权

US07294882B2 Non-volatile memory with asymmetrical doping profile 有权
标题翻译：具有不对称掺杂特性的非易失性存储器
公开(公告)号：US07294882B2
公开(公告)日：2007-11-13
申请号：US10952689
申请日：2004-09-28
申请人： Gerrit Jan Hemink , Shinji Sato
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.
摘要翻译：在衬底上产生用于NAND串的堆叠栅极结构。以与堆叠的栅极结构之间的区域的第一注入角度进行源植入。排水注入以与叠置的栅极结构之间的区域的第二注入角度进行。漏极注入在堆叠栅极结构的漏极侧的衬底中产生第一导电类型的较低掺杂区域。源极注入在层叠栅极结构的源极侧的衬底中产生第一导电类型的较高掺杂区域。

46. 发明授权

US08593871B2 Apparatus for reducing the impact of program disturb 有权
公开(公告)号：US08593871B2
公开(公告)日：2013-11-26
申请号：US13588196
申请日：2012-08-17
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

47. 发明申请

US20130250690A1 SELECTED WORD LINE DEPENDENT SELECT GATE VOLTAGE DURING PROGRAM 有权
标题翻译：在程序期间选择的字线相关选择门电压
公开(公告)号：US20130250690A1
公开(公告)日：2013-09-26
申请号：US13430502
申请日：2012-03-26
申请人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。这可以是源极侧或漏极侧选择晶体管。这可能会阻止或减少由于DIBL而导致的程序干扰。这也可以防止或减少由于GIDL可能导致的程序干扰。当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。

48. 发明申请

US20130250689A1 SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMMING 有权
标题翻译：在编程期间选择的字线相关选择门限扩展区域电压
公开(公告)号：US20130250689A1
公开(公告)日：2013-09-26
申请号：US13430494
申请日：2012-03-26
申请人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

49. 发明申请

US20130223155A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：US20130223155A1
公开(公告)日：2013-08-29
申请号：US13403934
申请日：2012-02-23
申请人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
发明人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
IPC分类号： G11C16/10
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

50. 发明申请

US20120314495A1 APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB 有权
标题翻译：减少程序干扰的影响的装置
公开(公告)号：US20120314495A1
公开(公告)日：2012-12-13
申请号：US13588196
申请日：2012-08-17
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/02 , G11C16/04 , G11C16/12
CPC分类号： G11C16/3418 , G11C16/3427
摘要： The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.
摘要翻译：在期望编程另一非易失性存储元件的程序操作期间未选择（或禁止）非易失性存储元件的无意编程被称为程序干扰。提出了一种用于编程和/或读取非易失性存储器的系统，其减少了编程干扰的影响。在一个实施例中，在编程过程期间，对于特定字线（或存储元件的其他分组）使用不同的验证电平。在另一个实施例中，在读取过程期间，不同的比较级别用于特定单词（或存储单元的其他分组）。

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