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41. 发明授权

US5140401A CMOS ESD protection circuit with parasitic SCR structures 失效
标题翻译：具有寄生SCR结构的CMOS ESD保护电路
公开(公告)号：US5140401A
公开(公告)日：1992-08-18
申请号：US674666
申请日：1991-03-25
申请人： Ming D. Ker , Chung Y. Lee , Chung Y. Wu , Joe Ko
发明人： Ming D. Ker , Chung Y. Lee , Chung Y. Wu , Joe Ko
IPC分类号： H01L27/02
CPC分类号： H01L27/0251
摘要： A circuit for protecting a CMOS device against execssive voltages has two SCR circuits in which the bipolar transistors are formed as parasitic devices. One SCR circuit is connected between a line to be protected and one power supply point and the other SCR circuit is connected between the line to be protected and the other power supply point. The power supply points form sinks for currents associated with excessive voltages, and they form reference potential points for establishing the voltage at which an SCR turns on. A semiconductor device having an n-substrate has three p-wells. The center p-well (as seen in section) forms part of two vertical transistors, one for each of the two SCR's. Each outer p-well cooperates with the center p-well and the intervening substrate to form a lateral transistor for one of the SCR's. These transistors use shared semiconductor regions that establish the base to collector interconnections of an SCR. These regions and other structures also form an FET and a diode in each SCR circuit that turn on the SCR in response to an excessive voltage.
摘要翻译：用于保护CMOS器件免受执行电压的电路具有两个SCR电路，其中双极晶体管形成为寄生器件。一个SCR电路连接在要保护的线路和一个电源点之间，另一个SCR电路连接在要保护的线路和另一个电源点之间。电源点形成与过电压相关的电流的吸收点，并且它们形成用于建立SCR导通的电压的参考电位点。具有n衬底的半导体器件具有三个p阱。中心p阱（如部分所示）构成两个垂直晶体管的一部分，一个用于两个SCR的每一个。每个外部p阱与中心p阱和中间衬底配合以形成用于SCR之一的横向晶体管。这些晶体管使用建立SCR的基极到集电极互连的共享半导体区域。这些区域和其他结构还在每个SCR电路中形成FET和二极管，以响应于过高的电压而导通SCR。

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