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41. 发明授权

US06105125A High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information 失效
标题翻译：用于使用分割式微ROM访问的处理器的高速，可扩展的基于微码的指令解码器，动态通用微指令和具有预解码指令信息的微代码
公开(公告)号：US06105125A
公开(公告)日：2000-08-15
申请号：US968976
申请日：1997-11-12
申请人： Mario Nemirovsky , Shailaja Chenumalla
发明人： Mario Nemirovsky , Shailaja Chenumalla
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
CPC分类号： G06F9/30167 , G06F9/223 , G06F9/267 , G06F9/30145
摘要： A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster decode of the instruction. The present invention includes the decode of an instruction using an entry ROM, which contains information regarding the instruction that can directly be used in generating the decoder outputs. This information is also used in selecting the correct ROM entry, thus enhancing the flexibility of the decoder, and to dynamically generate a generic microcode entry. Thus, microcode space requirements are reduced. A generic microcode instruction is used for commonly used, similar macroinstructions. This avoids duplication of microcode instructions and thus reduces the required microcode space. The invention also includes the generation of a generic microinstruction dynamically by using the predecoded information selected from the entry microcode table. This makes the generic microinstruction flexible and hence, it can be efficiently be used for many instructions. An entry microcode table, used for the efficient decode of an instruction, contains predecoded information about the instruction apart from the regular microinstruction, which is used directly to generate the decoder outputs and to select the correct microcode entry, and also for the generation of the generic microcode entry. The invention also includes accessing the entry ROM and the .mu.ROM in parallel, using the same address which is generated from the opcode and ModR/M bytes, and selecting one of their outputs. Thus the two ROMs are used efficiently in that the required time and logic are reduced.
摘要翻译：一种用于微处理器的基于微码的解码器电路，其使用快速访问表来解码指令。指向表的指针直接从指令预取缓冲区生成。关于指令的信息位被添加到表中，而不需要额外的成本，并且使得能够更快地解码指令。本发明包括使用入口ROM的指令的解码，其包含关于可以直接用于生成解码器输出的指令的信息。该信息还用于选择正确的ROM条目，从而增强解码器的灵活性，并且动态地生成通用微代码条目。因此，减少了微代码空间的要求。通用的微代码指令用于常用的类似宏指令。这避免了微代码指令的重复，从而减少了所需的微代码空间。本发明还包括通过使用从入口微代码表中选择的预解码信息来动态地生成通用微指令。这使得通用微指令灵活，因此可以有效地用于许多指令。用于指令的有效解码的入口微代码表包含关于除常规微指令之外的指令的预解码信息，其直接用于生成解码器输出并选择正确的微代码条目，并且还用于生成通用微代码条目。本发明还包括使用从操作码和ModR / M字节产生的相同地址并且选择其输出之一并行地访问条目ROM和mu ROM。因此，有效地使用了两个ROM，因为减少了所需的时间和逻辑。

42. 发明授权

US5649147A Circuit for designating instruction pointers for use by a processor decoder 失效
标题翻译：用于指定处理器解码器使用的指令指针的电路
公开(公告)号：US5649147A
公开(公告)日：1997-07-15
申请号：US451495
申请日：1995-05-26
申请人： Christopher E. Phillips , Mario Nemirovsky
发明人： Christopher E. Phillips , Mario Nemirovsky
IPC分类号： G06F9/30 , G06F9/32 , G06F12/04
CPC分类号： G06F9/30149 , G06F9/32 , G06F9/321
摘要： A circuit designates the values of an M bit first pointer and of an N+M bit second pointer. A first register circuit network holds the M bit first pointer, and a second register circuit network into holds an M bit portion of the N+M bit second pointer. A third register circuit network holds the remaining N bit portion of the N+M bit second pointer. A combiner circuit network, connected to receive the M bit first pointer from the first register circuit network, combines the received M bit first pointer with an externally provided data element length value to generate a new M bit first pointer. The combiner circuit network selectively generates a carry signal. The new M bit first pointer is selectively provided for loading into the first register circuit network and for loading into the second register circuit network as the M bit portion of the N+M bit portion of the second pointer. The remaining N bit portion of the N+M bit second pointer is received from the third register circuit network and, in response to the carry signal, one of the received remaining N bit portion and a modified remaining N bit portion is provided as a new remaining N bit portion for loading the new remaining N bit portion into the third register circuit network.
摘要翻译：电路指定M位第一指针和N + M位第二指针的值。第一寄存器电路网络保持M位第一指针，并且第二寄存器电路网络保持N + M位第二指针的M位部分。第三寄存器电路网络保存N + M位第二指针的剩余N位部分。连接以从第一寄存器电路网络接收M位第一指针的组合器电路网络将接收的M位第一指针与外部提供的数据元素长度值组合，以生成新的M位第一指针。组合器电路网络选择性地产生进位信号。新的M位第一指针被选择性地提供用于加载到第一寄存器电路网络中，并且作为第二指针的N + M位部分的M位部分加载到第二寄存器电路网络中。从第三寄存器电路网络接收N + M位第二指针的剩余N位部分，并且响应于进位信号，将接收的剩余N位部分和修改的剩余N位部分中的一个作为新的剩余的N位部分用于将新的剩余N位部分加载到第三寄存器电路网络中。

43. 发明授权

US07661112B2 Methods and apparatus for managing a buffer of events in the background 有权
标题翻译：用于管理后台事件缓冲区的方法和装置
公开(公告)号：US07661112B2
公开(公告)日：2010-02-09
申请号：US11278747
申请日：2006-04-05
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/542 , G06F13/126 , G06F2209/544 , G06F2209/546
摘要： A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
摘要翻译：用于对具有处理器的数据处理系统中的事件进行排序和计费的后台事件缓冲器管理器（BEBM）包括用于从设备接收事件标识（ID）的端口，用于排队接收的事件ID的排队功能和通知功能用于通知处理器排队的事件ID。 BEBM处理处理器的所有事件排序和计费。优选实施例中的BEBM按照类型优先级和类型下的优先级排队事件，并且还处理在对每个事件的处理结束时向设备发送确认，并且缓冲确认过程。在特定实施例中，该装置和方法被教导为分组处理路由器引擎。

44. 发明授权

US07237093B1 Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams 有权
标题翻译：多线程处理器中的指令获取系统利用高速缓存未命中预测来从多个硬件流获取指令
公开(公告)号：US07237093B1
公开(公告)日：2007-06-26
申请号：US09595776
申请日：2000-06-16
申请人： Enric Musoll , Mario Nemirovsky
发明人： Enric Musoll , Mario Nemirovsky
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3844
摘要： In a multi-streaming processor having a memory cache, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and a hit/miss predictor for forecasting whether a load instruction will hit or miss the cache. The prediction by the hit-miss predictor is used by the fetch algorithm in determining from which stream to fetch. A hit prediction results in a next instruction being fetched from the same stream as the instruction tested by the hit/miss predictor, while a miss prediction results in the next instruction being fetched from a different stream, if any. The predictor is also used to determine which instructions to dispatch to functional units.
摘要翻译：在具有存储器高速缓存的多流处理器中，提供了用于从多个流中的各个流中取出指令到指令流水线的系统，其包括用于从哪个流中选择一个指令的提取算法，以及用于获取指令的命中/未命中预测器预测加载指令是否会击中或错过缓存。命中缺失预测器的预测由获取算法用于确定从哪个流获取。命中预测导致从与命中/未命中预测器测试的指令相同的流中获取下一条指令，而未命中预测则导致下一条指令从不同的流中取出（如果有的话）。预测器还用于确定哪些指令发送到功能单元。

45. 发明申请

US20060153197A1 Queueing system for processors in packet routing operations 有权
公开(公告)号：US20060153197A1
公开(公告)日：2006-07-13
申请号：US11360338
申请日：2006-02-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

46. 发明授权

US07058064B2 Queueing system for processors in packet routing operations 有权
公开(公告)号：US07058064B2
公开(公告)日：2006-06-06
申请号：US09737375
申请日：2000-12-14
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F13/00 , G06F12/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

47. 发明授权

US5042005A Timer channel with match recognition features 失效
标题翻译：定时器通道与匹配识别功能
公开(公告)号：US5042005A
公开(公告)日：1991-08-20
申请号：US234111
申请日：1988-08-19
申请人： Gary L. Miller , Vernon B. Goler , Mario Nemirovsky , Daniel N. DeBrito
发明人： Gary L. Miller , Vernon B. Goler , Mario Nemirovsky , Daniel N. DeBrito
IPC分类号： G06F1/14
CPC分类号： G06F1/14
摘要： A timer subsystem which provides a data processor servicing the timer subsystem with the ability to inhibit the match recognition logic of the timer subsystem while the processor is servicing the subsystem. The disclosed embodiment comprises a sixteen-channel timer subsystem with a dedicated service processor. The service processor, under control of the micro-coded programs executing thereon, is capable of disabling a match recognition latch in the timer channel currently being serviced. This feature provides the ability to prevent unwanted matches which occur while the service processor is updating the match register, for instance. Another feature of the timer subsystem is the inhibition of multiple matches to a single match register value by disabling the match recognition latch upon the occurrence of a match and re-enabling it only when the match register is written by the data processor.

48. 发明授权

US07551626B2 Queueing system for processors in packet routing operations 有权
标题翻译：分组路由操作中处理器的排队系统
公开(公告)号：US07551626B2
公开(公告)日：2009-06-23
申请号：US11360338
申请日：2006-02-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F3/00 , G06F13/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
摘要翻译：在数据包处理器中，用于处理期间的分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动已识别分组的处理，完成的分组的下载或用于重新选择所选分组标识符的选择逻辑。

49. 发明申请

US20070294702A1 METHOD AND APPARATUS FOR IMPLEMENTING ATOMICITY OF MEMORY OPERATIONS IN DYNAMIC MULTI-STREAMING PROCESSORS 有权
标题翻译：在动态多流程处理器中实现存储器操作原理的方法和装置
公开(公告)号：US20070294702A1
公开(公告)日：2007-12-20
申请号：US11676541
申请日：2007-02-20
申请人： Stephen Melvin , Mario Nemirovsky
发明人： Stephen Melvin , Mario Nemirovsky
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087
摘要： A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism operating to set a lock when an atomic memory sequence is started and to clear a lock when an atomic memory sequence is completed. In preferred embodiments the lock mechanism comprises one or more storage locations associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.
摘要翻译：多流处理器具有用于流式传输一个或多个指令线程的多个流，用于处理来自流的指令的一组功能资源，以及用于锁定由处理器的流共享的所选择的存储器位置的锁定机构，硬件锁定机构操作在原子存储器序列启动时设置锁定，并且当原子存储器序列完成时清除锁定。在优选实施例中，锁定机构包括与处理器的每个流相关联的一个或多个存储位置，每个存储位置能够存储存储器地址锁定位和失速位。还教导了使用该装置实施本发明的方法。

50. 发明申请

US20070061619A1 INTERRUPT AND EXCEPTION HANDLING FOR MULTI-STREAMING DIGITAL PROCESSORS 有权
标题翻译：多流数字处理器的中断处理和异常处理
公开(公告)号：US20070061619A1
公开(公告)日：2007-03-15
申请号：US11277101
申请日：2006-03-21
申请人： Mario Nemirovsky , Adolfo Nemirovsky , Nerendra Sankar
发明人： Mario Nemirovsky , Adolfo Nemirovsky , Nerendra Sankar
IPC分类号： G06F11/00
CPC分类号： G06F9/4818
摘要： A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt.
摘要翻译：多流处理器具有用于流式传输一个或多个指令线程的多个流，用于处理来自流的指令的一组功能资源以及中断处理程序逻辑。该逻辑检测并将中断和异常映射到一个或多个特定流。在一些实施例中，一个中断或异常可以被映射到两个或更多个流，并且在另一个实施例中，两个或多个中断或异常可被映射到一个流。映射可以是静态的，并且在处理器设计，可编程的情况下确定，数据存储和修改，或条件和动态，中断逻辑执行对变量敏感的算法以确定映射。中断可能是由活动流生成的处理器软件（内部）中断产生的外部中断或基于变量的有条件的中断。中断被确认中断或异常映射到的流被定向到适当的服务程序。在同步方法中，不会发生矢量化，直到映射中断的所有流确认中断。

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