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41. 发明申请

US20120147649A1 Non-Volatile Memory Having 3d Array of Read/Write Elements with Low Current Structures and Methods Thereof 有权
标题翻译：具有3d阵列的具有低电流结构的读/写元件的非易失性存储器及其方法
公开(公告)号：US20120147649A1
公开(公告)日：2012-06-14
申请号：US13323766
申请日：2011-12-12
申请人： George Samachisa , Johann Alsmeier
发明人： George Samachisa , Johann Alsmeier
IPC分类号： G11C5/02 , H01L21/8239
CPC分类号： H01L27/11551 , G11C5/025 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2213/71 , H01L21/306 , H01L21/76224 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/1226 , H01L45/1273 , H01L45/144 , H01L45/146 , H01L45/149 , H01L45/1616
摘要： A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size.
摘要翻译：在位于半导体衬底上方不同距离的多个平面层上形成三维阵列读/写（R / W）存储元件。优选以低电流和高电阻状态操作R / W元件。这些电阻状态的电阻也取决于R / W元件的尺寸，并且由工艺技术预先确定。与R / W元件串联的片状电极及其形成方法提供了另一个自由度来调整R / W存储元件的电阻。调整片状电极的厚度，以便在从字线到位线的电路中获得减小的截面接触。这允许R / W存储元件具有大大增加的电阻，因此以大大减小的电流工作。片状电极形成的电池尺寸几乎没有增加。

42. 发明授权

US5428621A Latent defect handling in EEPROM devices 失效
标题翻译： EEPROM器件中的潜在缺陷处理
公开(公告)号：US5428621A
公开(公告)日：1995-06-27
申请号：US948175
申请日：1992-09-21
申请人： Sanjay Mehrotra , Winston Lee , George Samachisa , Stephen J. Gross
发明人： Sanjay Mehrotra , Winston Lee , George Samachisa , Stephen J. Gross
IPC分类号： G01R31/28 , G06F11/10 , G06F12/16 , G11C16/06 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/50 , G06F11/00
CPC分类号： G11C29/76 , G11C29/02 , G11C29/025 , G11C29/50 , G11C29/82 , G11C29/832 , G11C29/88 , G06F11/1008 , G11C16/04 , G11C2029/5006
摘要： A memory system having a two dimensional array of EEPROM or Flash EEPROM cells is addressable by rows and columns. A word line is connected to the control gates of all the cells in each row, an erase line is connected to all the erase gates of each sector of cells, and a pair of bit lines are connected respectively to all the sources and drains of each column of cells. The memory system incorporates a word line current detector and an erase line current detector in addition to the usual bit line current detectors. The leakage current of each of the lines are measured after predetermined memory events such as program or erase operations. When a defective row or column is detected, it is electrically isolated from other columns by programming and is mapped out and replaced. Data recovery schemes include reading a defective column by a switched-memory-source-drain technique.
摘要翻译：具有EEPROM或闪存EEPROM单元的二维阵列的存储器系统可由行和列寻址。字线连接到每行的所有单元的控制栅极，擦除线连接到每个单元扇区的所有擦除栅极，并且一对位线分别连接到每个单元的所有源和漏极细胞柱。存储器系统除了通常的位线电流检测器之外还包括字线电流检测器和擦除线电流检测器。在预定的存储器事件例如编程或擦除操作之后测量每条线路的漏电流。当检测到有缺陷的行或列时，通过编程与其他列电隔离，并进行映射和更换。数据恢复方案包括通过开关式存储器 - 源极 - 漏极技术读取有缺陷的列。

43. 发明授权

US08576651B2 Temperature compensation of conductive bridge memory arrays 有权
公开(公告)号：US08576651B2
公开(公告)日：2013-11-05
申请号：US13354796
申请日：2012-01-20
申请人： Roy E. Scheuerlein , George Samachisa
发明人： Roy E. Scheuerlein , George Samachisa
IPC分类号： G11C7/04 , G11C5/14
CPC分类号： G11C11/5642 , G11C5/02 , G11C5/063 , G11C5/14 , G11C7/00 , G11C7/04 , G11C7/12 , G11C8/08 , G11C13/0004 , G11C13/0011 , G11C13/0035 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2029/1204 , G11C2213/71 , G11C2213/77
摘要： Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

44. 发明申请

US20130188431A1 TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS 有权
标题翻译：导电桥记忆阵列的温度补偿
公开(公告)号：US20130188431A1
公开(公告)日：2013-07-25
申请号：US13354796
申请日：2012-01-20
申请人： Roy E. Scheuerlein , George Samachisa
发明人： Roy E. Scheuerlein , George Samachisa
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C11/5642 , G11C5/02 , G11C5/063 , G11C5/14 , G11C7/00 , G11C7/04 , G11C7/12 , G11C8/08 , G11C13/0004 , G11C13/0011 , G11C13/0035 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2029/1204 , G11C2213/71 , G11C2213/77
摘要： Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.
摘要翻译：描述了用于操作包括基于与半导体存储器阵列相关联的一个或多个阵列条件动态调整控制线电压（例如，未选择的字线或未选择的位线电压）的半导体存储器阵列的方法。一个或多个阵列条件可以包括与半导体存储器阵列相关联的温度或与半导体存储器阵列相关联的特定数量的写周期。在一些实施例中，基于一个或多个阵列条件产生中间电压并施加到半导体存储器阵列的未选字线和未选位线。可以产生一个或多个中间电压，使得共享所选字线的未选择的存储单元之间的第一电压差与基于一个或多个阵列条件共享所选位线的其他未选择存储单元之间的第二电压差不同。

45. 发明申请

US20120120710A1 MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATRIE POLARITY 有权
标题翻译：具有可逆电阻切换的存储器系统使用ALTERNATRI极性脉冲
公开(公告)号：US20120120710A1
公开(公告)日：2012-05-17
申请号：US12948375
申请日：2010-11-17
申请人： Peter Rabkin , George Samachisa , Roy E. Scheuerlein
发明人： Peter Rabkin , George Samachisa , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/009 , G11C2013/0092 , G11C2213/72
摘要： A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.
摘要翻译：存储器系统包括多个非易失性存储元件，每个非易失性存储元件包括与可逆电阻切换材料串联的二极管（或其他转向装置）。存储器系统中的一个或多个电路通过将一个或多个非易失性存储元件的可逆电阻切换材料改变为第一电阻状态而对非易失性存储元件进行编程。存储系统还可以将一个或多个非易失性存储元件的可逆电阻切换材料从第一电阻状态改变到第二电阻状态，通过将一对或多对相反极性的电压条件（例如，脉冲）施加到相应的二极管（或其他转向装置）使得电流在二极管（或其他转向装置）中流动，而不会在击穿情况下操作二极管（或其他转向装置）。

46. 发明申请

US20110297912A1 Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof 审中-公开
标题翻译：具有3d阵列的具有垂直位线和横向对齐的有源元件的读/写元件的非易失性存储器及其方法
公开(公告)号：US20110297912A1
公开(公告)日：2011-12-08
申请号：US13151217
申请日：2011-06-01
申请人： George Samachisa , Johann Alsmeier
发明人： George Samachisa , Johann Alsmeier
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： G11C16/10 , G11C13/003 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/149
摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The memory elements of the multiple layers are formed simultaneously in an orientation parallel to the substrate thereby reducing processing cost. In another aspect, a diode is formed in series with each memory element to reduce current leakage. The diode is incorporated within a pillar line acting as a bit line without taking up additional space.
摘要翻译：存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。存储元件响应于在其上施加的电压差而可逆地改变电导级。三维阵列包括从基板通过多层平面的柱线的二维阵列，其中每个平面上的字线阵列被用于访问存储元件。多层的记忆元件以平行于基板的方向同时形成，从而降低了处理成本。在另一方面，与每个存储元件串联形成二极管以减少电流泄漏。二极管被并入在作为位线的柱线中，而不占用额外的空间。

47. 发明申请

US20110089391A1 PUNCH-THROUGH DIODE STEERING ELEMENT 有权
标题翻译： PUNCH-THROUGH二极管转向元件
公开(公告)号：US20110089391A1
公开(公告)日：2011-04-21
申请号：US12582509
申请日：2009-10-20
申请人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
发明人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
IPC分类号： H01L29/861 , H01L45/00 , H01L21/70
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.
摘要翻译：描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

48. 发明授权

US07830698B2 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US07830698B2
公开(公告)日：2010-11-09
申请号：US12153872
申请日：2008-05-27
申请人： Xiying Chen , Bing K. Yen , Dat Nguyen , Huiwen Xu , George Samachisa , Tanmay Kumar , Er-Xuan Ping
发明人： Xiying Chen , Bing K. Yen , Dat Nguyen , Huiwen Xu , George Samachisa , Tanmay Kumar , Er-Xuan Ping
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/00 , G11C13/0069 , G11C13/025 , G11C2013/009 , G11C2213/35 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/149 , H01L45/1616 , H01L45/1675
摘要： A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.
摘要翻译：非易失性存储单元包括与存储元件串联定位的转向元件。存储元件包括碳材料，并且存储单元包括具有多个存储器级别的可重写单元。

49. 发明授权

US06977844B2 Method of reducing disturbs in non-volatile memory 失效
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06977844B2
公开(公告)日：2005-12-20
申请号：US11054084
申请日：2005-02-08
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

50. 发明授权

US06888752B2 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US06888752B2
公开(公告)日：2005-05-03
申请号：US10613098
申请日：2003-07-01
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

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