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41. 发明授权

US07098521B2 Reduced guard ring in schottky barrier diode structure 失效
标题翻译：减少肖特基势垒二极管结构中的保护环
公开(公告)号：US07098521B2
公开(公告)日：2006-08-29
申请号：US10711744
申请日：2004-10-01
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Alvin J. Joseph , Robert M. Rassel
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Alvin J. Joseph , Robert M. Rassel
IPC分类号： H01L29/812
CPC分类号： H01L29/66143 , H01L29/0615 , H01L29/0692 , H01L29/872
摘要： Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integrated circuit device may reduce or eliminate parasitic capacitance by eliminating this guard ring.
摘要翻译：肖特基势垒二极管使用介电分离区域结合活性区域。电介质分离区允许在至少一个维度上消除保护环。此外，在集成电路器件的有源部分中使用介质分离区可以通过消除该保护环来减少或消除寄生电容。

42. 发明授权

US08609505B2 Method of forming MIM capacitor structure in FEOL 有权
标题翻译：在FEOL中形成MIM电容器结构的方法
公开(公告)号：US08609505B2
公开(公告)日：2013-12-17
申请号：US13359032
申请日：2012-01-26
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L27/06 , H01L27/07 , H01L21/20
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
摘要翻译：电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器由第二电容器板，电容器电介质层和半导体衬底形成。

43. 发明授权

US08207568B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08207568B2
公开(公告)日：2012-06-26
申请号：US11162661
申请日：2005-09-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/92
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：制造MIM电容器和MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

44. 发明申请

US20120122293A1 METHOD OF FORMING MIM CAPACITOR STRUCTURE IN FEOL 有权
标题翻译：在FEOL中形成MIM电容结构的方法
公开(公告)号：US20120122293A1
公开(公告)日：2012-05-17
申请号：US13359032
申请日：2012-01-26
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
摘要翻译：电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器由第二电容器板，电容器电介质层和半导体衬底形成。

45. 发明授权

US07919830B2 Method and structure for ballast resistor 有权
标题翻译：镇流电阻的方法和结构
公开(公告)号：US07919830B2
公开(公告)日：2011-04-05
申请号：US12062262
申请日：2008-04-03
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Kimball M. Watson
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Kimball M. Watson
IPC分类号： H01L21/8222
CPC分类号： H01L29/41708 , H01L27/0629 , H01L27/0658 , H01L29/66272 , H01L29/7322 , H01L29/78
摘要： A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.
摘要翻译：一种用于制造低电阻电阻器的方法，例如用于双极结型晶体管的镇流电阻器。可以使用适当的薄层电阻的层来制造电阻器，以便在紧凑的布局中实现低电阻值。该方法可以依赖于传统CMOS工艺流程已经提供的层，例如接触插塞和完全硅化（FUSI）金属栅极。

46. 发明申请

US20080258197A1 SEMICONDUCTOR-INSULATOR-SILICIDE CAPACITOR 失效
标题翻译：半导体 - 绝缘体 - 硅化物电容器
公开(公告)号：US20080258197A1
公开(公告)日：2008-10-23
申请号：US11737844
申请日：2007-04-20
申请人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
发明人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
IPC分类号： H01L21/20 , H01L29/04
CPC分类号： H01L29/94
摘要： A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.
摘要翻译：半导体绝缘体硅化物（SIS）电容器通过在硅化物掩模介电层上沉积薄硅层而形成，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化。含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。硅化物掩模介电层是电容器电介质。电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。

47. 发明申请

US20080124883A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
公开(公告)号：US20080124883A1
公开(公告)日：2008-05-29
申请号：US11941452
申请日：2007-11-16
申请人： Douglas D. COOLBAUGH , Alvin J. Joseph , Seong-dong Kim , Louis D. Laozerotti , Xuefeng Liu , Robert M. Rassel
发明人： Douglas D. COOLBAUGH , Alvin J. Joseph , Seong-dong Kim , Louis D. Laozerotti , Xuefeng Liu , Robert M. Rassel
IPC分类号： H01L21/8222
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

48. 发明授权

US07329940B2 Semiconductor structure and method of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US07329940B2
公开(公告)日：2008-02-12
申请号：US11163882
申请日：2005-11-02
申请人： Douglas D. Coolbaugh , Alvin J. Joseph , Seong-dong Kim , Louis D. Lanzerotti , Xuefeng Liu , Robert M. Rassel
发明人： Douglas D. Coolbaugh , Alvin J. Joseph , Seong-dong Kim , Louis D. Lanzerotti , Xuefeng Liu , Robert M. Rassel
IPC分类号： H01L27/082
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

49. 发明申请

US20100038750A1 Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors 有权
标题翻译：具有VIAS和高密度电容器的结构，设计结构和制造方法
公开(公告)号：US20100038750A1
公开(公告)日：2010-02-18
申请号：US12191385
申请日：2008-08-14
申请人： David S. Collins , Kai D. Feng , Zhong-Xiang Ile , Peter J. Lindgren , Robert M. Rassel
发明人： David S. Collins , Kai D. Feng , Zhong-Xiang Ile , Peter J. Lindgren , Robert M. Rassel
IPC分类号： H01L29/92 , G06F17/50
CPC分类号： H01L29/66181 , H01L29/945
摘要： A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.
摘要翻译：半导体结构和设计结构至少包括布置在衬底中的具有不同深度的第一沟槽和第二沟槽，布置在第一沟槽中的电容器和布置在第二沟槽中的通孔。

50. 发明授权

US08674423B2 Semiconductor structure having vias and high density capacitors 有权
标题翻译：具有通孔和高密度电容器的半导体结构
公开(公告)号：US08674423B2
公开(公告)日：2014-03-18
申请号：US13302168
申请日：2011-11-22
申请人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
发明人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译：制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。第一和第二沟槽在衬底中具有不同的深度。

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