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41. 发明授权

US06238971B1 Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures 失效
标题翻译：电容器结构，DRAM单元结构和集成电路，以及形成电容器结构，集成电路和DRAM单元结构的方法
公开(公告)号：US06238971B1
公开(公告)日：2001-05-29
申请号：US08798242
申请日：1997-02-11
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L21/76895 , H01L27/10811 , H01L27/10855 , H01L28/84 , Y10S438/964
摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node. The invention also includes a DRAM cell comprising: a) a bitline node and a capacitor node electrically connected together through a transistor gate; b) a capacitor electrically connected to the capacitor node, the capacitor comprising; i) a storage node, the storage node in lateral cross-section comprising an outer surface extending over a top of the storage node, along a pair of opposing lateral surfaces of the storage node, and within laterally opposing cavities beneath the storage node; ii) a dielectric layer against the storage node outer surface and extending within the opposing cavities beneath the storage node; and iii) a cell plate layer against the dielectric layer and extending within the opposing cavities beneath the storage node; and c) a bitline electrically connected to the bitline node.
摘要翻译：本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。本发明包括形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。本发明还包括DRAM单元，其包括：a）通过晶体管栅极电连接在一起的位线节点和电容器节点; b）电连接到所述电容器节点的电容器，所述电容器包括： i）存储节点，所述存储节点在横截面中包括沿着所述存储节点的一对相对的侧表面延伸到所述存储节点的顶部的外表面，以及在所述存储节点下方的横向相对的空腔内; ii）抵靠存储节点外表面并在存储节点下面的相对空腔内延伸的电介质层; 以及iii）抵靠所述电介质层并且在所述存储节点下方的相对空腔内延伸的电池板层; 以及c）与所述位线节点电连接的位线。

42. 发明授权

US06207523B1 Methods of forming capacitors DRAM arrays, and monolithic integrated circuits 失效
标题翻译：电容器，DRAM阵列，单片集成电路和形成电容器，DRAM阵列和单片集成电路的方法
公开(公告)号：US06207523B1
公开(公告)日：2001-03-27
申请号：US08887742
申请日：1997-07-03
申请人： Kunal R. Parekh , John K. Zahurak , Phillip G. Wald
发明人： Kunal R. Parekh , John K. Zahurak , Phillip G. Wald
IPC分类号： H01L2120
CPC分类号： H01L27/10888 , H01L27/10852 , H01L27/10855 , H01L28/82 , H01L28/84 , H01L28/90 , H01L29/94 , Y10S438/964
摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.
摘要翻译：本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

43. 发明授权

US6060351A Process for forming capacitor over bit line memory cell 失效
标题翻译：在位线存储单元上形成电容器的工艺
公开(公告)号：US6060351A
公开(公告)日：2000-05-09
申请号：US998023
申请日：1997-12-24
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L21/8242
CPC分类号： H01L27/10844 , H01L27/10852 , Y10S257/906
摘要： A stacked capacitor memory cell and method for its fabrication including providing a layer of insulation glass over word lines on a silicon semiconductor substrate; self-aligning contact holes at the storage nodes and bit line contact location; providing a blanket layer of polysilicon, then silicide, and then an insulating cap; removing a portion of the insulating cap, silicide and polysilicon to form polysilicon plugs having outward surfaces at an elevation below the surface of the insulating glass, thus forming the bit line, a bit line contact and isolating the storage nodes; and providing a stacked capacitor on top of the bit line and in electrical communication with the storage node contact location through the plugs formed simultaneously with the bit line and bit line contact.
摘要翻译：一种叠层电容器存储单元及其制造方法，包括在硅半导体衬底上的字线上提供绝缘玻璃层; 存储节点和位线接触位置处的自对准接触孔; 提供覆盖层的多晶硅，然后是硅化物，然后是绝缘帽; 去除绝缘帽，硅化物和多晶硅的一部分以形成在绝缘玻璃表面下方的外表面的多晶硅塞，从而形成位线，位线接触并隔离存储节点; 并且在位线顶部提供堆叠的电容器，并通过与位线和位线接触同时形成的插头与存储节点接触位置电连通。

44. 发明授权

US07718495B2 Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors 有权
标题翻译：形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法
公开(公告)号：US07718495B2
公开(公告)日：2010-05-18
申请号：US11849813
申请日：2007-09-04
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L21/00
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823425 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
摘要翻译：本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与在晶体管的栅极附近的各向异性蚀刻的侧壁间隔开。

45. 发明授权

US06500709B2 Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures 有权
标题翻译：电容器结构，DRAM单元结构和集成电路，以及形成电容器结构，集成电路和DRAM单元结构的方法
公开(公告)号：US06500709B2
公开(公告)日：2002-12-31
申请号：US09767480
申请日：2001-01-22
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L21/76895 , H01L27/10811 , H01L27/10855 , H01L28/84 , Y10S438/964
摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node. The invention also includes a DRAM cell comprising: a) a bitline node and a capacitor node electrically connected together through a transistor gate; b) a capacitor electrically connected to the capacitor node, the capacitor comprising; i) a storage node, the storage node in lateral cross-section comprising an outer surface extending over a top of the storage node, along a pair of opposing lateral surfaces of the storage node, and within laterally opposing cavities beneath the storage node; ii) a dielectric layer against the storage node outer surface and extending within the opposing cavities beneath the storage node; and iii) a cell plate layer against the dielectric layer and extending within the opposing cavities beneath the storage node; and c) a bitline electrically connected to the bitline node.
摘要翻译：本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。本发明包括一种形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。本发明还包括DRAM单元，其包括：a）通过晶体管栅极电连接在一起的位线节点和电容器节点; b）电连接到所述电容器节点的电容器，所述电容器包括： i）存储节点，所述存储节点在横截面中包括沿着所述存储节点的一对相对的侧表面延伸到所述存储节点的顶部的外表面，以及在所述存储节点下方的横向相对的空腔内; ii）抵靠存储节点外表面并在存储节点下面的相对空腔内延伸的电介质层; 以及iii）抵靠所述电介质层并且在所述存储节点下方的相对空腔内延伸的电池板层; 以及c）与所述位线节点电连接的位线。

46. 发明授权

US06383868B1 Methods for forming contact and container structures, and integrated circuit devices therefrom 有权
标题翻译：用于形成接触和容器结构的方法及其集成电路装置
公开(公告)号：US06383868B1
公开(公告)日：2002-05-07
申请号：US09653501
申请日：2000-08-31
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10811 , H01L27/10852 , H01L28/84 , H01L28/90
摘要： Methods for forming contact structures and container structures, as well as integrated circuits that can be formed by employing those methods are provided. The integrated circuitry formed by the methods of the present invention provide capacitors in containers having sufficiently high storage capacitance for advanced integrated circuit devices. In addition the methods for forming such container capacitors facilitate the formation of contacts structures and provided for the formation of local interconnect structures and electrical contact to each of the structures formed.
摘要翻译：提供形成接触结构和容器结构的方法以及可以通过采用这些方法形成的集成电路。通过本发明的方法形成的集成电路为先进的集成电路器件提供具有足够高的存储电容的容器中的电容器。此外，用于形成这种容器电容器的方法有助于形成接触结构并且提供用于形成局部互连结构和与形成的每个结构的电接触。

47. 发明授权

US06329682B1 Capacitor over bit line memory cell and process 有权
标题翻译：电容器在位线存储器单元和工艺
公开(公告)号：US06329682B1
公开(公告)日：2001-12-11
申请号：US09526559
申请日：2000-03-16
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L27108
CPC分类号： H01L27/10844 , H01L27/10852 , Y10S257/906
摘要： A stacked capacitor memory cell and method for its fabrication including providing a layer of insulation glass over word lines on a silicon semiconductor substrate; self-aligning contact holes at the storage nodes and bit line contact location; providing a blanket layer of polysilicon, then silicide, and then an insulating cap; removing a portion of the insulating cap, silicide and polysilicon to form polysilicon plugs having outward surfaces at an elevation below the surface of the insulating glass, thus forming the bit line, a bit line contact and isolating the storage nodes; and providing a stacked capacitor on top of the bit line and in electrical communication with the storage node contact location through the plugs formed simultaneously with the bit line and bit line contact.
摘要翻译：一种叠层电容器存储单元及其制造方法，包括在硅半导体衬底上的字线上提供绝缘玻璃层; 存储节点和位线接触位置处的自对准接触孔; 提供覆盖层的多晶硅，然后是硅化物，然后是绝缘帽; 去除绝缘帽，硅化物和多晶硅的一部分以形成在绝缘玻璃表面下方的外表面的多晶硅塞，从而形成位线，位线接触并隔离存储节点; 并且在位线顶部提供堆叠的电容器，并通过与位线和位线接触同时形成的插头与存储节点接触位置电连通。

48. 发明授权

US06228710B1 Methods of forming capacitors and DRAM arrays 失效
标题翻译：形成电容器和DRAM阵列的方法
公开(公告)号：US06228710B1
公开(公告)日：2001-05-08
申请号：US09291423
申请日：1999-04-13
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10888 , H01L28/84 , H01L28/87
摘要： The invention encompasses methods of forming DRAM constructions, methods of forming capacitor constructions, DRAM constructions, and capacitor constructions. The invention includes a method in which a) a first layer is formed over a node location; b) a semiconductive material masking layer is formed over the first layer; c) an opening is formed through the semiconductive material masking layer and the first layer to the node location; d) an upwardly open capacitor storage node layer is formed within the opening; e) a storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and a capacitor plate are formed over the storage node. The invention also includes a capacitor structure comprising: a) an insulative layer over a substrate; b) a polysilicon layer over the insulative layer; c) an opening extending through the polysilicon layer and the insulative layer to a node, the opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions; d) a spacer over the step; e) a storage node layer over the spacer, polysilicon layer and the node; and f) a dielectric layer and a cell plate layer capacitively coupled to the storage node layer.
摘要翻译：本发明包括形成DRAM结构的方法，形成电容器结构的方法，DRAM结构和电容器结构。本发明包括一种方法，其中a）在节点位置上形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过半导体材料掩蔽层和第一层到达节点位置形成开口; d）在开口内形成向上开放的电容器存储节点层; e）从掩蔽层和存储节点层形成存储节点; 以及f）在所述存储节点上形成电容器介电层和电容器板。本发明还包括电容器结构，包括：a）衬底上的绝缘层; b）绝缘层上的多晶硅层; c）延伸穿过所述多晶硅层和所述绝缘层到达节点的开口，所述开口包括上部和下部，所述上部包括第一最小横截面尺寸，并且所述下部包括第二最小横截面尺寸比第一最小横截面尺寸窄，该开口还包括在上部和下部的界面处的台阶; d）台阶上的间隔物; e）在所述间隔物，多晶硅层和所述节点之上的存储节点层; 以及f）电容耦合到存储节点层的电介质层和电池板层。

49. 发明授权

US5981333A Methods of forming capacitors and DRAM arrays 失效
标题翻译：形成电容器和DRAM阵列的方法
公开(公告)号：US5981333A
公开(公告)日：1999-11-09
申请号：US798879
申请日：1997-02-11
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10888 , H01L27/10811 , H01L28/84 , H01L28/87
摘要： The invention encompasses methods of forming DRAM constructions, methods of forming capacitor constructions, DRAM constructions, and capacitor constructions. The invention includes a method in which a) a first layer is formed over a node location; b) a semiconductive material masking layer is formed over the first layer; c) an opening is formed through the semiconductive material masking layer and the first layer to the node location; d) an upwardly open capacitor storage node layer is formed within the opening; e) a storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and a capacitor plate are formed over the storage node. The invention also includes a capacitor structure comprising: a) an insulative layer over a substrate; b) a polysilicon layer over the insulative layer; c) an opening extending through the polysilicon layer and the insulative layer to a node, the opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions; d) a spacer over the step; e) a storage node layer over the spacer, polysilicon layer and the node; and f) a dielectric layer and a cell plate layer capacitively coupled to the storage node layer.
摘要翻译：本发明包括形成DRAM结构的方法，形成电容器结构的方法，DRAM结构和电容器结构。本发明包括一种方法，其中a）在节点位置上形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过半导体材料掩蔽层和第一层到达节点位置形成开口; d）在开口内形成向上开放的电容器存储节点层; e）从掩蔽层和存储节点层形成存储节点; 以及f）在所述存储节点上形成电容器介电层和电容器板。本发明还包括电容器结构，包括：a）衬底上的绝缘层; b）绝缘层上的多晶硅层; c）延伸穿过所述多晶硅层和所述绝缘层到达节点的开口，所述开口包括上部和下部，所述上部包括第一最小横截面尺寸，并且所述下部包括第二最小横截面尺寸比第一最小横截面尺寸窄，该开口还包括在上部和下部的界面处的台阶; d）台阶上的间隔物; e）在所述间隔物，多晶硅层和所述节点之上的存储节点层; 以及f）电容耦合到存储节点层的电介质层和电池板层。

50. 发明授权

US06894332B2 Apparatus for reducing electrical shorts from the bit line to the cell plate 失效
标题翻译：用于减少从位线到单元板的电短路的装置
公开(公告)号：US06894332B2
公开(公告)日：2005-05-17
申请号：US09943778
申请日：2001-08-30
申请人： Kunal R. Parekh , Charles H. Dennison , Jeffrey W. Honeycutt
发明人： Kunal R. Parekh , Charles H. Dennison , Jeffrey W. Honeycutt
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/76802 , H01L21/76834 , H01L27/10852 , H01L28/84 , H01L28/91 , Y10S438/964
摘要： A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.
摘要翻译：在电容器电池板被蚀刻和清洁之后，沉积出四乙基正硅酸盐（TEOS）形式的应力缓冲器和掺杂剂阻挡层，从而消除从位线到电池板的电短路。

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