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41. 发明授权

US07623132B1 Programmable shader having register forwarding for reduced register-file bandwidth consumption 有权
标题翻译：可编程着色器具有寄存器转发功能，可减少寄存器文件带宽消耗
公开(公告)号：US07623132B1
公开(公告)日：2009-11-24
申请号：US11019975
申请日：2004-12-20
申请人： Rui M. Bastos , Christian Rouet , Emmett M. Kilgariff
发明人： Rui M. Bastos , Christian Rouet , Emmett M. Kilgariff
IPC分类号： G06T1/20 , G09G5/36
CPC分类号： G09G5/363 , G06T15/005 , G06T15/80 , G09G5/39
摘要： A method and apparatus of operating a shader having multiple texture or shader processing stations. That method includes feeding the output of a texture or shader processing station directly into the input of another texture or shader processing station. Further, only a subset of the processing stations has access to a shader register file.
摘要翻译：一种操作具有多个纹理或着色器处理站的着色器的方法和装置。该方法包括将纹理或着色器处理站的输出直接馈送到另一个纹理或着色器处理站的输入。此外，只有处理站的子集才能访问着色器寄存器文件。

42. 发明授权

US07486290B1 Graphical shader by using delay 有权
标题翻译：图形着色器使用延迟
公开(公告)号：US07486290B1
公开(公告)日：2009-02-03
申请号：US11149717
申请日：2005-06-10
申请人： Emmett M. Kilgariff , Rui M. Bastos , Wei-Chao Chen , Douglas J. Hahn
发明人： Emmett M. Kilgariff , Rui M. Bastos , Wei-Chao Chen , Douglas J. Hahn
IPC分类号： G06F15/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： A graphical shader and a method of distributing graphical data to shader pipelines in a graphical shader are disclosed. In accordance with the method, a shader pipeline input delay is set. Further, a group of the graphical data is distributed to a shader pipeline of the graphical shader to be processed. The method includes waiting for the shader pipeline input delay to elapse. After the shader pipeline input delay has elapsed, another group of the graphical data is distributed to another shader pipeline of the graphical shader to be processed. In another embodiment, a graphical shader includes a plurality of shader pipelines for processing graphical data. Further, the graphical shader includes a shader distributor for distributing a group of the graphical data to one of the shader pipelines and for distributing another group of the graphical data to another one of the shader pipelines after a shader pipeline input delay has elapsed.
摘要翻译：公开了一种图形着色器和在图形着色器中将图形数据分配到着色器管线的方法。根据该方法，设置着色器管线输入延迟。此外，一组图形数据被分配到要处理的图形着色器的着色器管线。该方法包括等待着色器流水线输入延迟过去。在着色器流水线输入延迟已经过去之后，另一组图形数据被分配到要处理的图形着色器的另一个着色器流水线。在另一个实施例中，图形着色器包括用于处理图形数据的多个着色器管线。此外，图形着色器包括着色器分配器，用于将一组图形数据分配到着色器管道中的一个，并且在着色器流水线输入延迟已经过去之后，将另一组图形数据分配给另一个着色器管线。

43. 发明授权

US07385607B2 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US07385607B2
公开(公告)日：2008-06-10
申请号：US10938042
申请日：2004-09-10
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
IPC分类号： G06F15/16 , G06F15/80 , G06T1/20
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

44. 发明授权

US07324113B1 Perspective correction computation optimization 有权
标题翻译：透视校正计算优化
公开(公告)号：US07324113B1
公开(公告)日：2008-01-29
申请号：US11076200
申请日：2005-03-09
申请人： Christian Rouet , Rui M. Bastos , Emmett M. Kilgariff
发明人： Christian Rouet , Rui M. Bastos , Emmett M. Kilgariff
IPC分类号： G06T1/00 , G09G5/00
CPC分类号： G06T15/005 , G09G5/005 , G09G5/363 , G09G5/393
摘要： A method of optimizing perspective correction computations to be executed in a programmable fragment shader, identifying a sequence of program instructions; determining whether the sequence of program instructions can be optimized based on the status of the bit; sourcing one or more interpolated texture map coordinates to thereby disable the perspective correction computation comprising division by (1/w); and enabling the optimized execution of one of a plurality of perspective computation functions by a sought operation in a shader unit without division of the interpolated texture maps coordinates by (1/w). The optimized function includes able mapping, projective mapping, normalization, or scaling invariant operations.
摘要翻译：一种优化在可编程片段着色器中执行的透视校正计算的方法，识别程序指令的序列; 确定是否可以基于位的状态来优化程序指令的序列; 提供一个或多个内插纹理贴图坐标，从而禁止包括除以（1 / w）的透视校正计算; 并且通过在着色器单元中的寻找操作来实现多个透视计算功能中的一个的优化执行，而不使内插纹理映射坐标乘以（1 / w）。优化的功能包括能够映射，投影映射，归一化或缩放不变操作。

45. 发明授权

US09536341B1 Distributing primitives to multiple rasterizers 有权
标题翻译：将原语分发到多个光栅化器
公开(公告)号：US09536341B1
公开(公告)日：2017-01-03
申请号：US12581746
申请日：2009-10-19
申请人： Johnny S. Rhoades , Emmett M. Kilgariff , Michael C. Shebanow , Ziyad S. Hakura , Dale L. Kirkland , James Daniel Kelly
发明人： Johnny S. Rhoades , Emmett M. Kilgariff , Michael C. Shebanow , Ziyad S. Hakura , Dale L. Kirkland , James Daniel Kelly
IPC分类号： G06F15/80 , G06T15/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
摘要翻译：本发明的一个实施例提出了一种用于将原语并行分配到多个光栅化器的技术。多个独立的几何单元在不同的图形基元上同时执行几何处理。原始分配方案以每个时钟的多个基元的速率将原始图元从多个几何单元同时传送到多个光栅化器。多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

46. 发明授权

US08930636B2 Relaxed coherency between different caches 有权
标题翻译：不同缓存之间轻松的一致性
公开(公告)号：US08930636B2
公开(公告)日：2015-01-06
申请号：US13555048
申请日：2012-07-20
申请人： Joel James McCormack , Rajesh Kota , Olivier Giroux , Emmett M. Kilgariff
发明人： Joel James McCormack , Rajesh Kota , Olivier Giroux , Emmett M. Kilgariff
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0815
摘要： One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.
摘要翻译：一个实施例提出了一种确保不同缓存之间的轻松一致性的技术。可以将两个不同的执行单元配置为访问可以存储对应于相同存储器地址的一个或多个高速缓存行的不同高速缓存。在存储器屏障指令之间的时间段期间，在不同的高速缓存之间保持轻松的一致性。更具体地，在第二高速缓存接收到也对应于特定存储器地址的读取或写入请求之前，对与特定存储器地址相对应的第一高速缓存中的高速缓存行的写入不一定被传播到第二高速缓存中的高速缓存行。因此，第一缓存和第二缓存在松弛一致性的时间段期间不一定是相干的。存储器障碍指令的执行确保在新的松弛一致性周期开始之前，不同的高速缓存将是相干的。

47. 发明授权

US08310482B1 Distributed calculation of plane equations 有权
标题翻译：平面方程的分布式计算
公开(公告)号：US08310482B1
公开(公告)日：2012-11-13
申请号：US12326051
申请日：2008-12-01
申请人： Ziyad S. Hakura , Emmett M. Kilgariff
发明人： Ziyad S. Hakura , Emmett M. Kilgariff
IPC分类号： G06T17/00
CPC分类号： G06T11/40 , G06T15/005 , G06T2200/28 , G06T2210/52
摘要： A system for distributed of plane equation calculations. A work distribution unit is configured to receive a set of vertex data that includes meta data associated with each vertex in a modeled three-dimensional scene, to divide the set of vertex data into a plurality of batches of vertices, and to distribute the plurality of batches of vertices to one or more general processing clusters (GPCs). A processing cluster array includes the one or more (GPCs), where each GPC includes one or more shader-primitive-controller units (SPMs), and each SPM is configured to calculate plane equation coefficients for a subset of the vertices included in a batch of vertices. Advantageously, a distributed configuration of multiple plane equation calculation units decreases the size of the data bus that carries plane equation coefficients and increases overall processing throughput.
摘要翻译：一种用于分布平面方程计算的系统。工作分配单元被配置为接收包括与建模的三维场景中的每个顶点相关联的元数据的一组顶点数据，以将顶点数据集合划分成多个顶点批次，并且将多个批次的顶点到一个或多个通用处理集群（GPC）。处理集群阵列包括一个或多个（GPC），其中每个GPC包括一个或多个着色器原始控制器单元（SPM），并且每个SPM被配置为计算包括在批处理中的顶点子集的平面方程系数的顶点。有利地，多平面方程计算单元的分布式配置减小了承载平面方程系数的数据总线的大小并且增加了总体处理吞吐量。

48. 发明申请

US20120026175A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20120026175A1
公开(公告)日：2012-02-02
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件多种图形操作与不同阶段的图形处理相关联。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

49. 发明授权

US08077174B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08077174B2
公开(公告)日：2011-12-13
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

50. 发明申请

US20110141122A1 DISTRIBUTED STREAM OUTPUT IN A PARALLEL PROCESSING UNIT 有权
标题翻译：并行处理单元中的分布式流输出
公开(公告)号：US20110141122A1
公开(公告)日：2011-06-16
申请号：US12894001
申请日：2010-09-29
申请人： Ziyad S. Hakura , Rohit Gupta , Michael C. Shebanow , Emmett M. Kilgariff
发明人： Ziyad S. Hakura , Rohit Gupta , Michael C. Shebanow , Emmett M. Kilgariff
IPC分类号： G06F15/80
CPC分类号： G06T1/00
摘要： A technique for performing stream output operations in a parallel processing system is disclosed. A stream synchronization unit is provided that enables the parallel processing unit to track batches of vertices being processed in a graphics processing pipeline. A plurality of stream output units is also provided, where each stream output unit writes vertex attribute data to one or more stream output buffers for a portion of the batches of vertices. A messaging protocol is implemented between the stream synchronization unit and the plurality of stream output units that ensures that each of the stream output units writes vertex attribute data for the particular batch of vertices distributed to that particular stream output unit in the same order in the stream output buffers as the order in which the batch of vertices was received from a device driver by the parallel processing unit.
摘要翻译：公开了一种用于在并行处理系统中执行流输出操作的技术。提供流同步单元，其使并行处理单元能够跟踪在图形处理流水线中正在处理的顶点的批次。还提供了多个流输出单元，其中每个流输出单元将顶点属性数据写入一批或多个顶点的一部分的流输出缓冲器。在流同步单元和多个流输出单元之间实现消息传递协议，确保每个流输出单元以流中相同的顺序写入分配给该特定流输出单元的特定批次的顶点的顶点属性数据输出缓冲器作为由并行处理单元从设备驱动器接收到顶点批次的顺序。

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