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41. 发明授权

US08049281B1 Symmetric non-intrusive and covert technique to render a transistor permanently non-operable 有权
标题翻译：对称非侵入和隐蔽技术使晶体管永久不可操作
公开(公告)号：US08049281B1
公开(公告)日：2011-11-01
申请号：US12960126
申请日：2010-12-03
申请人： Lap-Wai Chow , William M. Clark, Jr. , Gavin J. Harbison , Paul Ou Yang
发明人： Lap-Wai Chow , William M. Clark, Jr. , Gavin J. Harbison , Paul Ou Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L23/573 , H01L27/0203 , Y10S257/90
摘要： A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
摘要翻译：用于伪装集成电路结构的技术和结构。该技术包括形成第一导电类型的有源区和第二导电类型的LDD区，导致当标准电压施加到器件时总是不可操作的晶体管。

42. 发明授权

US07294935B2 Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide 有权
标题翻译：防止逆向工程的集成电路及使用端接在场氧化物上的表观金属接触线来制造其的方法
公开(公告)号：US07294935B2
公开(公告)日：2007-11-13
申请号：US09768904
申请日：2001-01-24
申请人： Lap-Wai Chow , James P. Baukus , William M. Clark, Jr.
发明人： Lap-Wai Chow , James P. Baukus , William M. Clark, Jr.
IPC分类号： H01L23/52 , H01L29/40
CPC分类号： H01L23/573 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricating such devices.
摘要翻译：半导体器件，包括集成电路，防止逆向工程，包括导致场氧化物的金属迹线。金属化通常导致电路的栅极，源极或漏极区域，而不是绝缘场氧化物，从而误导逆向工程师。一种制造这种装置的方法。

43. 发明授权

US06979606B2 Use of silicon block process step to camouflage a false transistor 有权
标题翻译：使用硅块工艺步骤来伪装假晶体管
公开(公告)号：US06979606B2
公开(公告)日：2005-12-27
申请号：US10637848
申请日：2003-08-07
申请人： Lap-Wai Chow , William M. Clark, Jr. , Gavin J. Harbison , James P. Baukus
发明人： Lap-Wai Chow , William M. Clark, Jr. , Gavin J. Harbison , James P. Baukus
IPC分类号： H01L23/58 , H01L27/02 , H01L21/338
CPC分类号： H01L23/573 , H01L27/02 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
摘要翻译：用于伪装集成电路结构的技术和结构。设置具有受控轮廓的导电材料层，以便当实际上该装置不可操作时，提供类似于可操作装置的导电材料的假象边缘。

44. 发明申请

US20050230787A1 Covert transformation of transistor properties as a circuit protection method 有权
标题翻译：晶体管属性的转换作为电路保护方法
公开(公告)号：US20050230787A1
公开(公告)日：2005-10-20
申请号：US10828022
申请日：2004-04-19
申请人： Lap-Wai Chow , William Clark , James Baukus
发明人： Lap-Wai Chow , William Clark , James Baukus
IPC分类号： H01L21/44 , H01L21/8238 , H01L27/02 , H01L27/092
CPC分类号： H01L21/823814 , H01L23/573 , H01L27/02 , H01L27/092
摘要： A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.
摘要翻译：用于伪装集成电路结构的技术和结构。该技术包括使用与有源区域相反类型的光密度掺杂剂（LDD）区域，导致当标准电压施加到器件时总是关闭的晶体管。

45. 发明授权

US06924552B2 Multilayered integrated circuit with extraneous conductive traces 失效
标题翻译：多层集成电路与外部导电迹线
公开(公告)号：US06924552B2
公开(公告)日：2005-08-02
申请号：US10686545
申请日：2003-10-14
申请人： James P. Baukus , Lap-Wai Chow , William M. Clark, Jr. , Paul Ou Yang
发明人： James P. Baukus , Lap-Wai Chow , William M. Clark, Jr. , Paul Ou Yang
IPC分类号： H01L23/04 , H01L23/48 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/58 , H01L27/02 , H01L29/40
CPC分类号： H01L27/0203 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.
摘要翻译：提供多层集成电路和设计多层集成电路的方法。电路包括放置在导电层中的至少两个导电层和外部导电线。外部导电线由与导电层中的材料相同的材料制成，其尺寸与导电层中材料的尺寸相同。外部导线执行对集成电路的操作不必要的功能，并且与功能导线不可区分，从而加重了逆向工程师的工作。设计多层电路的方法包括提供计算机生成的外部导电线的表示的步骤。

46. 发明授权

US06897535B2 Integrated circuit with reverse engineering protection 有权
标题翻译：具有逆向工程保护的集成电路
公开(公告)号：US06897535B2
公开(公告)日：2005-05-24
申请号：US10438689
申请日：2003-05-14
申请人： Lap-Wai Chow , William M. Clark, Jr. , James P. Baukus
发明人： Lap-Wai Chow , William M. Clark, Jr. , James P. Baukus
IPC分类号： H01L23/58 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.
摘要翻译：用于伪装集成电路结构的技术和结构。集成电路结构由具有受控轮廓和受控厚度的多层材料形成。在所述多个层之间设置受控厚度的介电材料层，从而使集成电路结构有意无法操作。

47. 发明授权

US06815816B1 Implanted hidden interconnections in a semiconductor device for preventing reverse engineering 失效
标题翻译：在半导体器件中隐藏的互连用于防止逆向工程
公开(公告)号：US06815816B1
公开(公告)日：2004-11-09
申请号：US09696826
申请日：2000-10-25
申请人： William M. Clark, Jr. , James P. Baukus , Lap-Wai Chow
发明人： William M. Clark, Jr. , James P. Baukus , Lap-Wai Chow
IPC分类号： H01L2348
CPC分类号： H01L27/02 , H01L21/743
摘要： A camouflaged interconnection for interconnecting two spaced-apart implanted regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first implanted region forming a conducting channel between the two spaced-apart implanted regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second implanted region of opposite conductivity to type, the second implanted region being disposed between the two spaced-apart implanted regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.
摘要翻译：一种用于在集成电路或器件中互连公共导电类型的两个间隔开的注入区域的伪装互连和其形成方法。伪装的互连包括在两个间隔开的注入区之间形成导电沟道的第一注入区，导电沟具有相同的共同导电类型并桥接两个间隔开的区之间的区域，导电类型，第二注入区域设置在两个间隔开的公共导电类型的注入区域之间，并且躺在导电沟道上以伪造导电沟道以进行逆向工程。

48. 发明授权

US06613661B1 Process for fabricating secure integrated circuit 失效
标题翻译：制造安全集成电路的过程
公开(公告)号：US06613661B1
公开(公告)日：2003-09-02
申请号：US09607009
申请日：2000-06-29
申请人： James P. Baukus , William M. Clark, Jr. , Lap-Wai Chow , Allan R. Kramer
发明人： James P. Baukus , William M. Clark, Jr. , Lap-Wai Chow , Allan R. Kramer
IPC分类号： H01L2144
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.
摘要翻译：通过将类似导电性的掺杂电路元件与衬底中的掺杂注入相连而不是金属化互连来保护集成电路免于逆向工程。掺杂电路元件及其对应的注入互连可以在具有公共注入掩模的公共制造步骤中形成，使得它们具有类似掺杂剂浓度的整体结构。衬底表面之上的金属化可被设计成提供互连的进一步屏蔽，并且微桥可以被添加到在互连路径中跨越晶体管栅极材料的条带。

49. 发明授权

US06459629B1 Memory with a bit line block and/or a word line block for preventing reverse engineering 有权
标题翻译：具有位线块和/或字线块的存储器用于防止逆向工程
公开(公告)号：US06459629B1
公开(公告)日：2002-10-01
申请号：US09848564
申请日：2001-05-03
申请人： William M. Clark, Jr. , James P. Baukus , Lap-Wai Chow
发明人： William M. Clark, Jr. , James P. Baukus , Lap-Wai Chow
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/12 , G11C7/24 , G11C16/22 , H01L27/02
摘要： A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.
摘要翻译：一种用于阻止未经授权的访问半导体存储器中的至少一个存储单元的方法和电路。该方法包括提供在要阻止对至少一个存储器单元的访问时呈现打开状态的开关和/或链接; 以及响应于所述开关或链路假定为打开状态，将与所述至少一个存储器单元相关联的数据线耦合到恒定电压源。

50. 发明授权

US5991209A Split sense amplifier and staging buffer for wide memory architecture 失效
标题翻译：分辨率放大器和分段缓冲器，适用于宽内存架构
公开(公告)号：US5991209A
公开(公告)日：1999-11-23
申请号：US827856
申请日：1997-04-11
申请人： Lap-Wai Chow
发明人： Lap-Wai Chow
IPC分类号： G11C7/06 , G11C16/04
CPC分类号： G11C7/065
摘要： In an amplifier design for a wide memory architecture, a staging buffer can be integrated with the final stage of a multi-stage sense amplifier. The staging buffer includes a memory latch for storing at least one bit of data. The data is transferred into the staging buffer from memory upon strobing at least one read enable line, and transferred from the staging buffer to a data bus upon strobing at least one write enable line. The data signal is transferred from the memory to the staging buffer at a voltage level lower than the full swing voltage level. The memory architecture produced using this design technique allows for a much lower voltage swing on all of the data lines, thus lowering the power requirements of the circuit.
摘要翻译：在用于宽存储器架构的放大器设计中，分级缓冲器可以与多级读出放大器的最后级集成。分级缓冲器包括用于存储至少一位数据的存储器锁存器。在选通至少一个读使能线时，数据从存储器传送到暂存缓冲器中，并且在选通至少一个写使能线时从数据总线传送到数据总线。数据信号在低于全摆幅电压电平的电压电平下从存储器传送到分段缓冲器。使用这种设计技术生产的存储架构允许在所有数据线上实现更低的电压摆幅，从而降低电路的功率需求。

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