专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08605528B2 Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods 失效
标题翻译：具有隔离预充电架构的感测放大器，结合了这种读出放大器的存储电路和相关联的方法
公开(公告)号：US08605528B2
公开(公告)日：2013-12-10
申请号：US13288424
申请日：2011-11-03
申请人： John E. Barth, Jr. , Donald W. Plass , Adis Vehabovic
发明人： John E. Barth, Jr. , Donald W. Plass , Adis Vehabovic
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C11/4091
摘要： Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods.
摘要翻译：公开了一种读出放大器和包含它的存储器电路。放大器包括交叉耦合的反相器，每个具有串联的下拉晶体管和上拉晶体管。一个逆变器具有控制晶体管的漏极节点之间的电连接的电压控制开关。在读操作期间，上拉晶体管漏极节点被预充电为高电平，并且下拉晶体管漏极节点接收输入信号。开关跳闸，从而仅在下拉式晶体管漏极节点处的电压小于开关跳闸电压时进行电气连接。在这种情况下，感测节点放电到与输入信号相同的电平。否则，交换机可防止电气连接，并且感测节点保持高电平。跳闸电压取决于可以变化的参考电压，从而允许选择性地调节读出放大器的灵敏度。还公开了相关联的方法。

42. 发明授权

US08492819B2 FET eDRAM trench self-aligned to buried strap 失效
标题翻译： FET eDRAM沟槽自对准到掩埋带
公开(公告)号：US08492819B2
公开(公告)日：2013-07-23
申请号：US13182738
申请日：2011-07-14
申请人： Brent A. Anderson , John E. Barth, Jr. , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John E. Barth, Jr. , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/06 , H01L21/20
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087
摘要： A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array.
摘要翻译：一种制造场效应晶体管（FET）嵌入式动态随机存取存储器（eDRAM）单元阵列的结构和方法，其包括：延伸到绝缘体上硅（SOI）的掩埋氧化物（BOX）层的掩埋硅带，基质; 向下延伸到SOI衬底的衬底层的凹陷沟槽电容器; 形成在所述凹槽沟槽电容器上的导电顶板的与所述掩埋硅带的第一侧表面接触的侧表面; 设置在导电顶板上方的电介质盖; 由所述SOI衬底的硅层形成的第一FET，其中所述第一FET的源极/漏极区域接触所述埋入硅带的第二侧表面; 以及经过的字线，设置在电介质盖的与埋置硅带相对并分离并连接到FET eDRAM单元阵列的相邻行中的第二FET的栅极的部分上。

43. 发明授权

US08227310B2 Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact and methods of making 有权
标题翻译：集成电路包括通过上覆触点电连接到沟槽电容器的有源晶体管和制造方法
公开(公告)号：US08227310B2
公开(公告)日：2012-07-24
申请号：US12186780
申请日：2008-08-06
申请人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L21/76895 , H01L23/485 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated circuit.
摘要翻译：一种形成集成电路的方法包括：提供半导体形貌，其包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着外围设置用于隔离沟槽电容器的沟槽电容器; 在半导体形貌上形成层间电介质; 同时蚀刻（i）通过层间电介质到有源晶体管和沟槽电容器的漏极结的第一开口，以及（ii）通过层间电介质到有源晶体管的源极结的第二开口; 以及用导电材料填充第一开口和第二开口以形成用于将沟槽电容器电连接到有源晶体管的漏极结的带，并且还形成用于将源极结连接到集成的上覆层电路。

44. 发明授权

US08080851B2 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 有权
标题翻译：用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管
公开(公告)号：US08080851B2
公开(公告)日：2011-12-20
申请号：US12201462
申请日：2008-08-29
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L23/62
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：公开了半导体结构。半导体结构包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层设置在掩埋绝缘体层正下方并形成导电路径的第二极性类型的带区域，设置在本体衬底中并与带区接触的第二极性类型的阱区，填充有导电的深沟槽设置在阱区内的第一极性类型的材料以及由深沟槽的下部和阱区之间的接合部限定的静电放电（ESD）保护二极管。

45. 发明授权

US07989893B2 SOI body contact using E-DRAM technology 有权
公开(公告)号：US07989893B2
公开(公告)日：2011-08-02
申请号：US12200482
申请日：2008-08-28
申请人： John E. Barth, Jr. , Kerry Bernstein , Francis R. White
发明人： John E. Barth, Jr. , Kerry Bernstein , Francis R. White
IPC分类号： H01L27/01 , H01L29/786
CPC分类号： H01L29/78615
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.

46. 发明授权

US07898078B1 Power connector/decoupler integrated in a heat sink 有权
标题翻译：集成在散热器中的电源连接器/解耦器
公开(公告)号：US07898078B1
公开(公告)日：2011-03-01
申请号：US12568837
申请日：2009-09-29
申请人： Kerry Bernstein , John E. Barth, Jr.
发明人： Kerry Bernstein , John E. Barth, Jr.
IPC分类号： H01L23/36
CPC分类号： H01L23/5286 , H01L23/36 , H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06589 , H01L2924/1305 , H01L2924/00
摘要： Two sets of conductor fins are formed on a topmost surface of stacked semiconductor chips. The two sets of conductor fins are electrically isolated from each other, and function as radiators that dissipate heat from the stacked semiconductor chips. Conductive wiring structures are formed on each set of conductor fins to supply electrical power and electrical grounding to the stacked semiconductor chips. The bottommost surface of the stacked semiconductor chips may be bonded to a packaging substrate. Since the semiconductor fins above provide electrical power supply and electrical grounding, a higher fraction of electrical connections between the bottommost surface of the stacked semiconductor chips and the packaging substrate may be employed for input and output signal transmission without adverse impact on heat dissipation of the stacked semiconductor chips. The conductive fins function as power connectors. Decoupling capacitors including the conductive fins and dielectric portions therebetween may be formed.
摘要翻译：在堆叠的半导体芯片的最上表面上形成两组导体散热片。这两组导体翅片彼此电隔离，并且用作散发来自堆叠的半导体芯片的热量的散热器。在每组导体翅片上形成导电布线结构，以向堆叠的半导体芯片提供电力和电气接地。堆叠的半导体芯片的最底表面可以结合到封装衬底。由于上述半导体鳍片提供电力供应和电气接地，堆叠的半导体芯片的最底部表面和封装衬底之间的电连接的较高部分可用于输入和输出信号传输，而不会对堆叠的半导体芯片的散热产生不利影响半导体芯片。导电翅片用作电源连接器。可以形成包括其间的导电翅片和电介质部分的去耦电容器。

47. 发明授权

US07791977B2 Design structure for low overhead switched header power savings apparatus 失效
标题翻译：低开销交换机头节能设备的设计结构
公开(公告)号：US07791977B2
公开(公告)日：2010-09-07
申请号：US12116322
申请日：2008-05-07
申请人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
发明人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147 , G11C5/148 , G11C8/12
摘要： A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于减少存储器阵列中的漏电流的三态电源门控装置。所述装置包括耦合到所述存储器阵列的第一分配报头装置，所述第一分配报头装置被配置为限制通过所述存储器阵列的泄漏电流; 以及头部驱动器，其可操作地耦合到所述第一分配报头装置，用于实现所述第一分配报头装置的三态操作，其中三态操作包括睡眠模式，唤醒模式和保持模式。

48. 发明授权

US07791123B2 Soft error protection structure employing a deep trench 失效
标题翻译：采用深沟槽的软错误保护结构
公开(公告)号：US07791123B2
公开(公告)日：2010-09-07
申请号：US12045190
申请日：2008-03-10
申请人： Ethan H. Cannon , John E. Barth, Jr. , Kerry Bernstein
发明人： Ethan H. Cannon , John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L27/108
CPC分类号： H01L29/66181 , G11C5/005 , H01L21/765 , H01L27/0629 , H01L27/11 , H01L29/945
摘要： A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conductivity type. A doped well of the second conductivity type abutting the buried plate layer is formed. The doped semiconductor fill portion functions as a temporary reservoir for electrical charges of the first conductivity type that are generated by a radiation particle, and the buried plate layer functions as a temporary reservoir for electrical charges of the second conductivity type. The buried plate layer and the doped semiconductor fill portion forms a capacitor, and provides protection from soft errors to devices formed in the semiconductor layer or the doped well.
摘要翻译：在具有第一导电类型的掺杂的半导体层中形成包含掺杂半导体填充部分的深沟槽，该掺杂半导体填充部分具有第一导电类型掺杂并被由下部具有第二导电类型掺杂的掩埋板包围。形成与掩埋板层相邻的第二导电类型的掺杂阱。掺杂半导体填充部分用作由辐射颗粒产生的第一导电类型的电荷的临时储存器，并且掩埋板层用作第二导电类型的电荷的临时储存器。掩埋板层和掺杂半导体填充部分形成电容器，并且提供对软错误的保护以防止在半导体层或掺杂阱中形成的器件。

49. 发明授权

US07724565B2 Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices 失效
标题翻译：使用PFET接入器件的SRAM单元中小信号感测的装置和方法
公开(公告)号：US07724565B2
公开(公告)日：2010-05-25
申请号：US11850992
申请日：2007-09-06
申请人： John E. Barth, Jr. , Geordie M. Braceras , Harold Pilo
发明人： John E. Barth, Jr. , Geordie M. Braceras , Harold Pilo
IPC分类号： G11C7/12 , G11C11/41 , G11C11/419 , G11C7/06
CPC分类号： G11C7/12 , G11C7/22 , G11C11/413 , G11C2207/005
摘要： A design structure embodied in a machine readable medium used in a design process for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.
摘要翻译：在静态随机存取存储器（SRAM）单元的读取操作期间，在用于小信号感测的设计过程中使用的机器可读介质中的设计结构包括将一对互补读出放大器数据线耦合到相应的一对互补位线与SRAM单元相关联，以及设置读出放大器以放大在读出放大器数据线上产生的信号，其中位线对在读出放大器设置时保持耦合到读出放大器数据线。

50. 发明授权

US07061793B2 Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices 失效
标题翻译：使用PFET接入器件的SRAM单元中小信号感测的装置和方法
公开(公告)号：US07061793B2
公开(公告)日：2006-06-13
申请号：US10708713
申请日：2004-03-19
申请人： John E. Barth, Jr. , George M. Braceras , Harold Pilo
发明人： John E. Barth, Jr. , George M. Braceras , Harold Pilo
IPC分类号： G11C7/12 , G11C11/41 , G11C11/419 , G11C7/06
CPC分类号： G11C11/412
摘要： A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.
摘要翻译：在静态随机存取存储器（SRAM）单元的读取操作期间用于小信号感测的方法包括将一对互补读出放大器数据线耦合到与SRAM单元相关联的对应的一对互补位线，并且将读出放大器设置为放大在感测放大器数据线上产生的信号，其中位线对在读出放大器设置时保持耦合到读出放大器数据线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式