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41. 发明申请

US20050169419A1 Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector 有权
$Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector$
标题翻译：具有分数 - 频间隔相位频率检测器的分数整数锁相环系统
公开(公告)号：US20050169419A1
公开(公告)日：2005-08-04
申请号：US10770186
申请日：2004-02-02
申请人： John Melanson
发明人： John Melanson
IPC分类号： H03K21/00 , H03K23/54 , H03K23/68
CPC分类号： H03K23/68 , H03K23/546
摘要： A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.
摘要翻译：锁相环电路具有分频间隔相位频率检测器，电荷泵，振荡器和分频器。分数 - 频率间隔相位频率检测器具有用作多个相位频率检测器单元或由多个相位频率检测器单元使用的相位频率检测器单元。分频器响应于振荡器，并提供用于将振荡器频率除以分频值的分频器值，以提供锁相环电路的反馈环路信号的反馈频率。参考输入频率作为第一输入输入到相位频率检测器单元中。反馈频率作为第二输入被输入并选择性地延迟到相位频率检测器单元中，使得第二输入根据参考输入频率对准输入，并且振荡器频率实际上响应于相位频率检测器单元并允许由分数整数除法器值除。

42. 发明申请

US20050162286A1 Pattern biasing for look-ahead delta sigma modulators 有权
标题翻译：模式偏置用于先行的delta-Σ调制器
公开(公告)号：US20050162286A1
公开(公告)日：2005-07-28
申请号：US11043720
申请日：2005-01-26
申请人： John Melanson
发明人： John Melanson
IPC分类号： H03M3/00 , H03M7/00
CPC分类号： H03M7/3011 , H03M3/366 , H03M3/458
摘要： Look-ahead delta sigma modulators of a signal processing system can selectively bias one or more output candidate vectors to alter the probability of selecting a biased output candidate vector(s) for determination of a quantization output value. The probability, within a range of error, of certain output candidate vectors being selected by a quantizer of the look-ahead delta sigma modulator can be determined. The output candidate vectors determine the quantization output values. Thus, altering the probability of selecting a certain output candidate(s) alters the probability of occurrence of a certain quantization output value(s). Detection of the altered probability allows an output signal to be identified. Identifying an output signal allows for many interesting operations including identifying a specific signal processing system source of the output signal and modifying processing of the output signal. Additionally, some quantization output values can be compressed more densely than others.
摘要翻译：信号处理系统的前瞻三角Σ调制器可以选择性地偏置一个或多个输出候选向量以改变选择用于确定量化输出值的偏置输出候选矢量的概率。可以确定由前视δ-Σ调制器的量化器选择的某些输出候选向量在误差范围内的概率。输出候选矢量确定量化输出值。因此，改变选择某个输出候选者的概率改变某个量化输出值的出现概率。检测到改变的概率允许识别输出信号。识别输出信号允许许多有趣的操作，包括识别输出信号的特定信号处理系统源和修改输出信号的处理。另外，一些量化输出值可以被压缩得比其他的更密集。

43. 发明申请

US20050156770A1 Jointly nonlinear delta sigma modulators 有权
标题翻译：联合非线性ΔΣ调制器
公开(公告)号：US20050156770A1
公开(公告)日：2005-07-21
申请号：US11035288
申请日：2005-01-13
申请人： John Melanson
发明人： John Melanson
IPC分类号： H03M3/00 , H03M3/02 , H03M7/32
CPC分类号： H03M7/3013 , H03M7/3011 , H03M7/3028 , H03M7/304
摘要： A signal processing system includes a jointly non-linear delta sigma modulator. In one embodiment, the jointly non-linear delta sigma modulator includes a non-linear quantization transfer function, and the output of the delta sigma modulator is defined, at least in part, by a non-linear interrelationship of multiple noise-shaping filter state variables. A look-ahead delta-sigma modulator can be implemented as a noise shaping filter and a function generator. State variables of the noise shaping filter provide the input data from which the function generator determines a quantizer output signal. Latter state variables are more dominant in determining the quantizer output signal. Accordingly, earlier state variables can be approximated to a greater degree than latter state variables without significant compromise in quantization accuracy.
摘要翻译：信号处理系统包括联合非线性Δ-Σ调制器。在一个实施例中，联合非线性Δ-Σ调制器包括非线性量化传递函数，并且ΔΣ调制器的输出至少部分地由多个噪声整形滤波器状态的非线性相互关系变量。先行的delta-sigma调制器可以被实现为噪声整形滤波器和函数发生器。噪声整形滤波器的状态变量提供函数发生器从该输入数据确定量化器输出信号的输入数据。后期状态变量在确定量化器输出信号时更为主导。因此，较早的状态变量可以比后一种状态变量更大程度地近似，而量化精度没有显着的折中。

44. 发明申请

US20050062550A1 Low-noise loop filter for a phase-locked loop system 有权
标题翻译：用于锁相环系统的低噪声环路滤波器
公开(公告)号：US20050062550A1
公开(公告)日：2005-03-24
申请号：US10665164
申请日：2003-09-18
申请人： John Melanson
发明人： John Melanson
IPC分类号： H03L7/00 , H03L7/089 , H03L7/093 , H03L7/18
CPC分类号： H03L7/093 , H03L7/0891 , H03L7/18
摘要： A loop filter device and method for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes an integral path circuit and a new proportional path circuit cascaded together in series and further includes a summer. The integral path circuit integrates a loop filter input signal to provide an integrated signal that tracks an overall input signal level. The new proportional path circuit differentiates the integrated signal to provide a proportional signal based on a detected instantaneous phase difference for locking a frequency of a signal for a phase locked loop (PLL) circuit to a reference frequency. The summer receives as inputs and sums the integrated signal and the proportional signal to provide a low-noise loop filter output signal.
摘要翻译：公开了一种用于将信号的频率锁定到参考频率的锁相环（“PLL”）电路的环路滤波器装置和方法。环路滤波器包括串联级联在一起的积分路径电路和新的比例路径电路，还包括一个夏季。积分路径电路集成了环路滤波器输入信号，以提供跟踪整体输入信号电平的积分信号。新的比例路径电路基于检测到的瞬时相位差来区分积分信号以提供比例信号，用于将用于锁相环（PLL）电路的信号的频率锁定到参考频率。夏季作为输入接收积分信号和比例信号，以提供低噪声环路滤波器输出信号。

45. 发明授权

US06741197B1 Digital-to-analog converter (DAC) output stage 有权
标题翻译：数模转换器（DAC）输出级
公开(公告)号：US06741197B1
公开(公告)日：2004-05-25
申请号：US10341640
申请日：2003-01-13
申请人： John Melanson
发明人： John Melanson
IPC分类号： H03M166
CPC分类号： H03M3/502 , H03M7/3022
摘要： A digital-to-analog converter (DAC) output stage has an operational amplifier, an integrating path, a direct or data path, and a differentiated path. The integrating path is coupled in parallel to the operational amplifier. Each of the ends of the integrating path is respectively coupled to an input and an output of the operational amplifier. The direct or data path samples data during a first time sampling phase and is coupled in parallel with the integrating path during a second time sampling phase. The differentiated path is coupled in series with a data input voltage to the input of the operational amplifier.
摘要翻译：数模转换器（DAC）输出级具有运算放大器，积分路径，直接或数据路径以及微分路径。积分路径与运算放大器并联耦合。积分路径的每一端分别耦合到运算放大器的输入和输出端。直接或数据路径在第一时间采样阶段采样数据，并且在第二时间采样阶段期间与积分路径并联耦合。差分路径与数据输入电压串联耦合到运算放大器的输入端。

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