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41. 外观设计

USD777716S1 Case for electronic devices 有权
公开(公告)号：USD777716S1
公开(公告)日：2017-01-31
申请号：US29518089
申请日：2015-02-19
申请人： Dae-Young Kim
设计人： Dae-Young Kim

42. 外观设计

USD771608S1 Case for electronic device 有权
公开(公告)号：USD771608S1
公开(公告)日：2016-11-15
申请号：US29497570
申请日：2014-07-25
申请人： Dae-Young Kim , Soo Ha Jung
设计人： Dae-Young Kim , Soo Ha Jung

43. 外观设计

USD767573S1 Case for wrist-worn electronic device having a front enclosure member and a body enclosure member 有权
标题翻译：具有前壳体构件和主体外壳构件的腕部佩戴的电子装置的壳体
公开(公告)号：USD767573S1
公开(公告)日：2016-09-27
申请号：US29524722
申请日：2015-04-22
申请人： Dae-Young Kim
设计人： Dae-Young Kim

44. 外观设计

USD756367S1 Stand for electronic device 有权
公开(公告)号：USD756367S1
公开(公告)日：2016-05-17
申请号：US29529399
申请日：2015-06-05
申请人： Dae-Young Kim
设计人： Dae-Young Kim

45. 外观设计

USD753099S1 Case for an electronic communications device 有权
标题翻译：电子通讯设备案例
公开(公告)号：USD753099S1
公开(公告)日：2016-04-05
申请号：US29511948
申请日：2014-12-15
申请人： Dae-Young Kim
设计人： Dae-Young Kim

46. 外观设计

USD746805S1 Case for an electronic communications device 有权
公开(公告)号：USD746805S1
公开(公告)日：2016-01-05
申请号：US29511582
申请日：2014-12-11
申请人： Dae-Young Kim
设计人： Dae-Young Kim

47. 发明授权

US08395908B2 Semiconductor package and plasma display device including the same 失效
标题翻译：半导体封装和等离子体显示装置包括它们
公开(公告)号：US08395908B2
公开(公告)日：2013-03-12
申请号：US12654171
申请日：2009-12-11
申请人： Dae-Young Kim
发明人： Dae-Young Kim
IPC分类号： H05K7/02
CPC分类号： H01L23/49572 , H01L23/3121 , H01L23/49833 , H01L23/4985 , H01L24/28 , H01L24/48 , H01L24/49 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/48237 , H01L2224/4911 , H01L2224/73265 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/181 , H01L2924/19107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Provided are a semiconductor package and a plasma display device including the same. The semiconductor package includes a film substrate that relays a signal between a circuit board and a display panel; a semiconductor chip that is electrically connected to the film substrate; a reinforcement plate to which the film substrate and the semiconductor chip are connected to via adhesive layers, and that provides a floating ground; and a connecting member that electrically connects the reinforcement plate and a ground of the semiconductor chip, and that electrically connects the reinforcement plate and a ground of the film substrate. Accordingly, the semiconductor package has excellent heat dissipation performance and ground stability.
摘要翻译：提供一种半导体封装和包括该半导体封装的等离子体显示装置。半导体封装包括在电路板和显示面板之间中继信号的膜基板; 与薄膜基板电连接的半导体芯片; 加强板，薄膜基板和半导体芯片经由粘合层连接到该加强板，并且提供浮动接地; 以及连接构件，其电连接所述加强板和所述半导体芯片的接地，并且将所述加强板和所述薄膜基板的接地电连接。因此，半导体封装具有优异的散热性能和接地稳定性。

48. 发明申请

US20120040241A1 COPPER FOIL FOR CURRENT COLLECTOR OF LITHIUM SECONDARY BATTERY 审中-公开
标题翻译：锂二次电池电流收集器铜箔
公开(公告)号：US20120040241A1
公开(公告)日：2012-02-16
申请号：US12962180
申请日：2010-12-07
申请人： Dae-Young Kim , Byoung-Kwang Lee , Seung-Jun Choi
发明人： Dae-Young Kim , Byoung-Kwang Lee , Seung-Jun Choi
IPC分类号： H01M4/66
CPC分类号： H01M4/661 , C23F15/00 , C25D1/04 , C25D3/38 , H01M4/75 , H01M10/0525
摘要： A copper foil for a current collector of a lithium secondary battery is configured such that a nodule cluster having an inter-nodule aspect ratio of 0.001 to 2 is provided at a matte side formed on one surface of the copper foil, in aspect of a crystal structure, a ratio of a texture coefficient of a (200) surface to a sum of texture coefficients of a (111) surface and the (200) surface is 30 to 80%, the copper foil has a water contact angle of 90° or below, and impurity spots existing at the surface of the copper foil have a maximum diameter of 100 μm or less, and a minimal spacing distance between the impurity spots is 1 cm or more.
摘要翻译：另外，作为锂二次电池用集电体的铜箔，在铜箔的一面形成的无光泽面上设置结晶长宽比为0.001〜2的结核团，（200）表面的织构系数与（111）面和（200）表面的织构系数之和的比例为30〜80％，铜箔的接触角为90°，并且存在于铜箔表面的杂质点的最大直径为100μm以下，杂质点之间的最小间隔距离为1cm以上。

49. 发明授权

US07582563B2 Method for fabricating fully silicided gate 有权
标题翻译：完全硅化栅的制造方法
公开(公告)号：US07582563B2
公开(公告)日：2009-09-01
申请号：US11639257
申请日：2006-12-15
申请人： Dae-Young Kim , Han-Choon Lee
发明人： Dae-Young Kim , Han-Choon Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/28097
摘要： A method for fabricating a fully silicided gate, including forming a gate dielectric layer on a semiconductor substrate, depositing an amorphous silicon layer on the gate dielectric layer, forming a metallic layer on the amorphous silicon layer, depositing a hard mask on the metallic layer, wherein the amorphous silicon layer and the metal layer are silicided due to a thermal budget applied thereto, thereby forming a metal silicide layer, and patterning the metal silicide layer based on the hard mask to form a gate.
摘要翻译：一种制造完全硅化栅的方法，包括在半导体衬底上形成栅介电层，在栅介电层上沉积非晶硅层，在非晶硅层上形成金属层，在金属层上沉积硬掩模，其中由于施加到其上的热预算，非晶硅层和金属层被硅化，从而形成金属硅化物层，并且基于硬掩模构图金属硅化物层以形成栅极。

50. 发明申请

US20090039422A1 RECESS GATE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体器件的闭合栅及其形成方法
公开(公告)号：US20090039422A1
公开(公告)日：2009-02-12
申请号：US12188164
申请日：2008-08-07
申请人： Dae-Young Kim
发明人： Dae-Young Kim
IPC分类号： H01L21/28 , H01L29/78 , H01L21/67
CPC分类号： H01L29/1037 , H01L29/66553 , H01L29/66583 , H01L29/66621
摘要： A method for fabricating a semiconductor device, and more particularly, a method for forming a recess gate is disclosed. The method for forming a recess gate includes forming a first nitride layer over a semiconductor substrate, forming a first nitride layer pattern by selectively etching the first nitride layer to expose a portion of the substrate, forming a spacer over a sidewall of the first nitride layer pattern, forming a recess for a gate channel region by etching the substrate using the first nitride layer pattern and the spacer as an etching mask, forming a gate oxide layer over a sidewall and a bottom surface of the recess, forming a gate poly-silicon layer pattern to bury the recess and a space defined by the spacer, and removing the first nitride layer pattern.
摘要翻译：公开了一种用于制造半导体器件的方法，更具体地说，涉及一种用于形成凹槽的方法。形成凹槽的方法包括在半导体衬底上形成第一氮化物层，通过选择性地蚀刻第一氮化物层以暴露衬底的一部分形成第一氮化物层图案，在第一氮化物层的侧壁上形成间隔物通过使用第一氮化物层图案和间隔物作为蚀刻掩模蚀刻衬底，形成用于栅极沟道区的凹部，在凹部的侧壁和底表面上形成栅氧化层，形成栅极多晶硅以掩埋凹部和由间隔物限定的空间，以及去除第一氮化物层图案。

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