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41. 发明授权

US07595251B2 Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby 有权
标题翻译：制造具有对准键的半导体器件和由此制造的半导体器件的方法
公开(公告)号：US07595251B2
公开(公告)日：2009-09-29
申请号：US12325694
申请日：2008-12-01
申请人： Min-Hee Cho , Yoo-Sang Hwang , Byung-Hyun Lee
发明人： Min-Hee Cho , Yoo-Sang Hwang , Byung-Hyun Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/10894 , H01L23/544 , H01L27/10814 , H01L28/91 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.
摘要翻译：在制造具有对准键和由此制造的半导体器件的半导体器件的方法中。制造半导体器件的方法包括提供具有划线通道区域和单元区域的半导体衬底。蚀刻阻挡图案和栅极图案分别形成在划线路区域和单元区域上。形成第一层间绝缘层以覆盖蚀刻阻挡图案和栅极图案。分别在划线路区域和单元区域的第一层间绝缘层上形成初步对准键图案和位线图案。形成第二层间绝缘层以覆盖初步对准键图案和位线图案。将第二层间绝缘层和第一层间绝缘层图案化以暴露蚀刻阻挡图案，从而在划线路区域中形成对准键图案，同时在单元区域中形成存储节点接触开口。

42. 发明授权

US07262108B2 Methods for forming resistors for integrated circuit devices 有权
标题翻译：用于形成集成电路器件的电阻器的方法
公开(公告)号：US07262108B2
公开(公告)日：2007-08-28
申请号：US10961896
申请日：2004-10-08
申请人： Je-Min Park , Yoo-Sang Hwang
发明人： Je-Min Park , Yoo-Sang Hwang
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L21/76838 , H01L27/0629
摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.
摘要翻译：形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间导电层和绝缘层。此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分以前暴露在洞里。

43. 发明授权

US07176552B2 Semiconductor memory device having a decoupling capacitor 失效
标题翻译：具有去耦电容器的半导体存储器件
公开(公告)号：US07176552B2
公开(公告)日：2007-02-13
申请号：US11154922
申请日：2005-06-16
申请人： Je-Min Park , Yoo-Sang Hwang
发明人： Je-Min Park , Yoo-Sang Hwang
IPC分类号： H01L29/00
CPC分类号： H01L27/10855 , H01L27/0207 , H01L27/10894 , H01L28/91
摘要： A semiconductor memory device comprises a cell capacitor having a first buried contact connected with a semiconductor substrate of a cell region and a first storage node connected with the first buried contact, and a decoupling capacitor for reducing a coupling noise, having a plurality of second buried contacts formed on a semiconductor substrate portion adjacent in the cell region and extended in parallel with each other and a plurality of second storage nodes connected with the second buried contacts.
摘要翻译：半导体存储器件包括具有与单元区域的半导体衬底连接的第一埋入触点和与第一埋入触点连接的第一存储节点的单元电容器，以及用于降低耦合噪声的去耦电容器，具有多个第二埋入形成在与单元区域相邻并且彼此平行延伸的半导体衬底部分上的触点以及与第二埋入触点连接的多个第二存储节点。

44. 发明授权

US07078292B2 Storage node contact forming method and structure for use in semiconductor memory 有权
标题翻译：用于半导体存储器的存储节点接触形成方法和结构
公开(公告)号：US07078292B2
公开(公告)日：2006-07-18
申请号：US10875004
申请日：2004-06-22
申请人： Je-Min Park , Yoo-Sang Hwang , Cheol-Ju Yun
发明人： Je-Min Park , Yoo-Sang Hwang , Cheol-Ju Yun
IPC分类号： H01L21/8242
CPC分类号： H01L27/10855 , H01L27/10814 , H01L28/91
摘要： A storage node contact forming method and structure reduces the number of processes required by the conventional art and increases a critical dimension of a storage node to prevent a leaning phenomenon and reduce a manufacturing cost of semiconductor memory devices. The method includes preparing a semiconductor substrate that involves at least one contact pad contacted with an active region of a memory cell transistor through an insulation layer. The method also includes forming a storage node contact of T-shape, the storage node contact being composed of a lower region contacted with an upper part of the contact pad, and an upper region that is extended to a gate length direction of the memory cell transistor and that is formed as a size larger than a size of the lower region, in order to electrically connect the contact pad with a storage node to be formed in a later process.
摘要翻译：存储节点接触形成方法和结构减少了传统技术所需的处理次数，并且增加了存储节点的临界尺寸以防止倾斜现象并降低半导体存储器件的制造成本。该方法包括制备半导体衬底，其包括通过绝缘层与存储单元晶体管的有源区接触的至少一个接触焊盘。该方法还包括形成T形的存储节点接触，所述存储节点接触由与所述接触焊盘的上部接触的下部区域和延伸到所述存储单元的栅极长度方向的上部区域晶体管，并且形成为大于下部区域的尺寸的尺寸，以便将接触焊盘与要在稍后的工艺中形成的存储节点电连接。

45. 发明申请

US20060138513A1 Capacitors for semiconductor memory devices and methods of forming the same 有权
标题翻译：用于半导体存储器件的电容器及其形成方法
公开(公告)号：US20060138513A1
公开(公告)日：2006-06-29
申请号：US11316166
申请日：2005-12-22
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

46. 发明申请

US20060060945A1 Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby 有权
公开(公告)号：US20060060945A1
公开(公告)日：2006-03-23
申请号：US11232666
申请日：2005-09-22
申请人： Min-Hee Cho , Yoo-Sang Hwang , Byung Hyun Lee
发明人： Min-Hee Cho , Yoo-Sang Hwang , Byung Hyun Lee
IPC分类号： H01L29/06 , H01L21/8242
CPC分类号： H01L27/10894 , H01L23/544 , H01L27/10814 , H01L28/91 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.

47. 发明申请

US20060040454A1 Semiconductor devices having DRAM cells and methods of fabricating the same 有权
标题翻译：具有DRAM单元的半导体器件及其制造方法
公开(公告)号：US20060040454A1
公开(公告)日：2006-02-23
申请号：US11252963
申请日：2005-10-17
申请人： Je-Min Park , Yoo-Sang Hwang
发明人： Je-Min Park , Yoo-Sang Hwang
IPC分类号： H01L21/331
CPC分类号： H01L28/91 , H01L21/76895 , H01L27/0207 , H01L27/10814 , H01L27/10855
摘要： A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patterns are disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.
摘要翻译：半导体器件包括位线着陆焊盘和设置在覆盖衬底的位线着色焊盘的两侧上的存储着陆焊盘。位线层间绝缘层覆盖位线和存储着陆焊盘。多个位线图案设置在位线层间绝缘层上。位线图案各自包括位线和位线覆盖层图案。线绝缘层图案被放置在位线层间绝缘层的顶表面上。上接触孔位于位线图案之间的区域中，高于位线的上表面。接触孔间隔件覆盖上接触孔的侧壁。下接触孔与上接触孔自对准并延伸穿过线绝缘层图案和位线层间绝缘层，从而暴露存储节点着陆焊盘。

48. 发明申请

US20060017118A1 Semiconductor device having spacer pattern and method of forming the same 审中-公开
标题翻译：具有间隔图案的半导体器件及其形成方法
公开(公告)号：US20060017118A1
公开(公告)日：2006-01-26
申请号：US11184855
申请日：2005-07-20
申请人： Je-Min Park , Yoo-Sang Hwang
发明人： Je-Min Park , Yoo-Sang Hwang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L27/10885 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device having a spacer pattern and methods of forming the same that includes a lower interconnection pattern on a semiconductor substrate. A lower interconnection spacer covers sidewalls of the lower interconnection pattern. Spacer patterns cover the lower interconnection spacer of the lower interconnection pattern and disposed on the semiconductor substrate. An upper interconnection pattern is formed between the spacer patterns.
摘要翻译：本发明提供一种具有间隔图案的半导体器件及其形成方法，其包括在半导体衬底上的下部互连图案。下互连间隔件覆盖下互连图案的侧壁。间隔图案覆盖下部互连图案的下部互连间隔件并且设置在半导体衬底上。在间隔物图案之间形成上部互连图案。

49. 发明申请

US20050142756A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050142756A1
公开(公告)日：2005-06-30
申请号：US11020827
申请日：2004-12-22
申请人： Je-Min Park , Dong-Won Shin , Yoo-Sang Hwang
发明人： Je-Min Park , Dong-Won Shin , Yoo-Sang Hwang
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L21/4763 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/76895 , H01L27/0629 , H01L27/10814 , H01L27/10885 , H01L27/10894
摘要： A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed therein, and forming both a first landing pad in the core region on the insulation layer and a second landing pad in the peripheral region, the first landing pad being overlapped with a part of a first conductive line. The invention reduces the contact resistance and prevents or minimizes a device failure caused by a misalignment, with the simplified process.
摘要翻译：制造半导体存储器件的方法和形成电阻器和蚀刻保护层的结构以降低接触电阻。根据本发明的制造半导体存储器件的方法包括在具有单元阵列区域，芯区域和周边区域的半导体衬底上形成绝缘层，每个晶体管阵列区域和外围区域具有形成在其中的至少一个晶体管，并且形成第一在绝缘层上的芯区域中的着陆焊盘和外围区域中的第二着陆焊盘，第一着陆焊盘与第一导电线的一部分重叠。本发明通过简化的过程降低了接触电阻并且防止或最小化由不对准引起的设备故障。

50. 发明申请

US20050095779A1 Methods for forming resistors for integrated circuit devices 有权
标题翻译：用于形成集成电路器件的电阻器的方法
公开(公告)号：US20050095779A1
公开(公告)日：2005-05-05
申请号：US10961896
申请日：2004-10-08
申请人： Je-Min Park , Yoo-Sang Hwang
发明人： Je-Min Park , Yoo-Sang Hwang
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L27/06 , H01L21/8234 , H01L21/20 , H01L23/48 , H01L29/40
CPC分类号： H01L28/20 , H01L21/76838 , H01L27/0629
摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.
摘要翻译：形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间导电层和绝缘层。此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分以前暴露在洞里。

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