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41. 发明申请

US20050034976A1 Method and apparatus for plating and polishing semiconductor substrate 有权
标题翻译：电镀和抛光半导体衬底的方法和装置
公开(公告)号：US20050034976A1
公开(公告)日：2005-02-17
申请号：US10946703
申请日：2004-09-21
申请人： Homayoun Talieh , Cyprian Uzoh
发明人： Homayoun Talieh , Cyprian Uzoh
IPC分类号： B24B37/16 , C25D5/06 , C25D5/22 , C25D7/12 , C25D17/00 , C25D17/12 , C25D17/14 , C25F7/00 , H01L21/288 , H01L21/304 , H01L21/3205 , H01L21/321 , C25D5/48
CPC分类号： B24B37/16 , C25D5/06 , C25D5/22 , C25D7/123 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/3212
摘要： The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate. Furthermore, the present invention provides a method and apparatus that plates/deposits and/or polishes a conductive material and improves the electrolyte mass transfer properties on a substrate using a novel anode assembly.
摘要翻译：本发明提供一种在半导体衬底上沉积/沉积导电材料然后抛光相同衬底的方法和装置。这通过在单个设备中提供多个室来实现，其中一个室可以用于电镀/沉积导电材料，并且另一个室可以用于抛光半导体衬底。电镀/沉积工艺可以使用刷镀或电化学机械沉积进行，并且可以使用电抛光或化学机械抛光进行抛光工艺。本发明还提供一种用于将导电材料间歇地施加到半导体衬底的方法和装置，并且当这种导电材料未被施加到衬底时也间歇地抛光衬底。此外，本发明提供了一种使用新型阳极组件对导电材料进行平板/沉积和/或抛光并改善基板上的电解质传质性质的方法和装置。

42. 发明授权

US06852630B2 Electroetching process and system 有权
标题翻译：电蚀过程和系统
公开(公告)号：US06852630B2
公开(公告)日：2005-02-08
申请号：US09841622
申请日：2001-04-23
申请人： Bulent M. Basol , Cyprian Uzoh , Halit N. Yakupoglu , Homayoun Talieh
发明人： Bulent M. Basol , Cyprian Uzoh , Halit N. Yakupoglu , Homayoun Talieh
IPC分类号： B23H5/08 , C25F3/14 , H01L21/288 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L21/302
CPC分类号： H01L21/32115 , B23H5/08 , C25F3/14 , H01L21/2885 , H01L21/32134 , H01L21/7684
摘要： A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.
摘要翻译：用于可选地沉积或蚀刻晶片层的系统包括与晶片相对的掩模板，掩模板具有将溶液输送到晶片的多个开口。电极组件具有第一电极部件和第二电极部件，该第二电极部件具有可操作地与晶片的周边部分和中心部分接合的通道。通道将解决方案传输到面罩。

43. 发明申请

US20130014979A1 Connector Structures and Methods 有权
标题翻译：连接器结构和方法
公开(公告)号：US20130014979A1
公开(公告)日：2013-01-17
申请号：US13183920
申请日：2011-07-15
申请人： Cyprian Uzoh , Craig Mitchell
发明人： Cyprian Uzoh , Craig Mitchell
IPC分类号： H05K1/09 , H05K3/10 , H05K1/00
CPC分类号： H01R13/03 , H05K1/09 , H05K3/282 , H05K3/4007 , H05K2201/0338 , H05K2201/09745 , Y10T29/49155
摘要： Electrical contacts comprising a surface with a plurality of cavities therein and their methods of manufacture and use.
摘要翻译：电触头包括其中具有多个空腔的表面及其制造和使用方法。

44. 发明申请

US20120326326A1 Systems and Methods for Producing Flat Surfaces in Interconnect Structures 有权
标题翻译：在互连结构中产生平坦表面的系统和方法
公开(公告)号：US20120326326A1
公开(公告)日：2012-12-27
申请号：US13168839
申请日：2011-06-24
申请人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed
发明人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/3212 , H01L21/32125 , H01L21/7684 , H01L21/76843 , H01L21/76852 , H01L21/7688 , H01L23/481 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
摘要翻译：提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

45. 发明申请

US20120325517A1 RELIABLE WIRE STRUCTURE AND METHOD 有权
标题翻译：可靠的电线结构和方法
公开(公告)号：US20120325517A1
公开(公告)日：2012-12-27
申请号：US13168675
申请日：2011-06-24
申请人： Cyprian Uzoh , Craig Mitchell
发明人： Cyprian Uzoh , Craig Mitchell
IPC分类号： H01B5/00 , H01B13/00
CPC分类号： H01B13/0036 , H01L24/43 , H01L24/45 , H01L2224/43 , H01L2224/43848 , H01L2224/45015 , H01L2224/45105 , H01L2224/45109 , H01L2224/45111 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45157 , H01L2224/4516 , H01L2224/45163 , H01L2224/4518 , H01L2224/45184 , H01L2224/45565 , H01L2224/45572 , H01L2224/45573 , H01L2224/45605 , H01L2224/45609 , H01L2224/45611 , H01L2224/45644 , H01L2224/45647 , H01L2224/45655 , H01L2224/45657 , H01L2224/4568 , H01L2224/45686 , H01L2224/45693 , H01L2224/45887 , H01L2224/45893 , H01L2224/48 , H01L2224/85207 , H01L2924/01015 , H01L2924/10253 , Y10T29/49117 , H01L2924/01074 , H01L2924/00014 , H01L2924/0132 , H01L2924/00 , H01L2924/013 , H01L2924/04642 , H01L2924/0503 , H01L2924/01005 , H01L2924/01006
摘要： A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have a different grain sizes. An average grain size of the core material may several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.
摘要翻译：公开了一种可被配置用于半导体器件的导线结构。线可以包括由导体材料形成的细长柔性芯和覆盖芯的外表面的覆层。包层可以是导体。在各个方面，包覆层和芯具有不同的晶粒尺寸。芯材的平均晶粒尺寸可以比包覆层材料的平均晶粒尺寸大几个数量级。包覆层可以是在其厚度上具有不同浓度的次要组分的合金。还公开了形成线结构的方法。

46. 发明授权

US07329335B2 Device providing electrical contact to the surface of a semiconductor workpiece during processing 有权
标题翻译：在处理过程中提供与半导体工件的表面的电接触的装置
公开(公告)号：US07329335B2
公开(公告)日：2008-02-12
申请号：US10459323
申请日：2003-06-10
申请人： Homayoun Talieh , Cyprian Uzoh , Bulent M. Basol
发明人： Homayoun Talieh , Cyprian Uzoh , Bulent M. Basol
IPC分类号： B23H3/00 , C25F3/30 , B23H7/12
CPC分类号： B23H3/04 , B23H5/08 , C25D5/08 , C25D17/00 , C25D17/001 , C25D17/005 , C25F7/00 , H01L21/2885
摘要： Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.
摘要翻译：可以通过包括第一和第二导电元件的特定装置来提供导电材料在包含导电材料的电解质的衬底的包括半导体晶片的表面上的基本均匀沉积。第一导电元件可以具有相同或不同构造的多个电触点，或者可以是导电焊盘的形式，并且可以在基本上所有的衬底表面上与衬底表面接触或以其他方式电互连。当在电解质与衬底表面和第二导电元件物理接触的同时在第一和第二导电元件之间施加电势时，导电材料沉积在衬底表面上。可以使施加在阳极和阴极之间的电压的极性反转，从而可以对沉积的导电材料进行电蚀刻。

47. 发明申请

US20070135022A1 Apparatus for reduction of defects in wet procssed layers 有权
标题翻译：用于减少湿底层缺陷的设备
公开(公告)号：US20070135022A1
公开(公告)日：2007-06-14
申请号：US11704631
申请日：2007-02-09
申请人： Bulent Basol , Cyprian Uzoh
发明人： Bulent Basol , Cyprian Uzoh
IPC分类号： B24B49/00
CPC分类号： B24B57/02 , B24B37/042 , C23C18/1617 , C23C18/38 , C25D7/123 , C25D21/04 , C25D21/18 , H01L21/2885
摘要： The present invention provides an apparatus for wet processing of a conductive layer using a degassed process solution such as a degassed electrochemical deposition solution, a degassed electrochemical polishing solution, a degassed deposition solution, and a degassed cleaning solution. The technique includes degassing the process solution before delivering the degassed process solution to a processing unit or degassing the process solution in situ, within the processing unit.
摘要翻译：本发明提供一种使用脱气的电解沉积溶液，脱气电化学抛光溶液，脱气沉积溶液和脱气清洗溶液等脱气工艺溶液对导电层进行湿法加工的设备。该技术包括在将脱气的处理溶液递送到处理单元之前对处理溶液进行脱气或在处理单元内原位脱气处理溶液。

48. 发明申请

US20060009033A1 Defect-free thin and planar film processing 审中-公开
标题翻译：无缺陷的薄和平面薄膜加工
公开(公告)号：US20060009033A1
公开(公告)日：2006-01-12
申请号：US11226511
申请日：2005-09-13
申请人： Bulent Basol , Cyprian Uzoh
发明人： Bulent Basol , Cyprian Uzoh
IPC分类号： H01L21/461 , C25D17/00
CPC分类号： C25D17/001 , C25D7/123 , H01L21/2885 , H01L21/32125 , H01L21/7684 , H01L21/76877
摘要： The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.
摘要翻译：本发明的方法在半导体晶片表面中形成铜互连。在该过程中，最初，在晶片的顶表面中提供窄且大的特征，然后通过使用电化学沉积工艺沉积初级铜层。初级铜层完全填满了特征，并在狭窄的特征上形成一个平坦的表面，在大的特征上形成一个非平面的表面。通过采用电化学机械沉积工艺，将二次铜层沉积在初级铜层上，以形成窄和大特征上的平面铜层。在该工艺步骤之后，使用电解抛光工艺来减小平面铜层的厚度。

49. 发明申请

US20060006060A1 Method and apparatus for processing a substrate with minimal edge exclusion 审中-公开
标题翻译：用于处理具有最小边缘排除的基板的方法和装置
公开(公告)号：US20060006060A1
公开(公告)日：2006-01-12
申请号：US11225913
申请日：2005-09-13
申请人： Bulent Basol , Cyprian Uzoh , Homayoun Talieh
发明人： Bulent Basol , Cyprian Uzoh , Homayoun Talieh
IPC分类号： C25D17/00
CPC分类号： C25D5/02 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/3212 , H01L21/76877
摘要： An apparatus for processing a material on a surface of a wafer having a diameter includes a cavity defined by a peripheral wall terminating at a peripheral edge and having at least one lateral dimension smaller than the wafer diameter and at least one lateral dimension larger than the wafer diameter and configured to hold a process solution proximate to the peripheral edge such that the process solution will always contact a first wafer surface region, a head configured to hold the wafer above the cavity peripheral edge so that the surface of the wafer faces the cavity, and an electrical contact member positioned outside the cavity peripheral wall and configured to contact a second wafer surface region where the lateral dimension of the cavity is smaller than the wafer diameter and to maintain electrical contact with the wafer when the wafer is moved relative to the contact member. Advantages of the invention include substantially full surface treatment of the wafer.
摘要翻译：一种用于处理具有直径的晶片表面上的材料的设备包括由外围壁限定的空腔，该外围壁终止于外围边缘并具有至少一个小于晶片直径的横向尺寸和至少一个大于晶片的横向尺寸并且被配置为将处理溶液保持靠近外围边缘，使得处理溶液将始终接触第一晶片表面区域，头部被配置为将晶片保持在空腔周边边缘上方，使得晶片的表面面向空腔，以及电接触构件，其定位在所述腔周壁外部并且被配置为接触所述腔的横向尺寸小于所述晶片直径的第二晶片表面区域，并且当所述晶片相对于所述触点移动时与所述晶片保持电接触会员。本发明的优点包括晶片的基本全表面处理。

50. 发明授权

US06943112B2 Defect-free thin and planar film processing 有权
标题翻译：无缺陷的薄和平面薄膜加工
公开(公告)号：US06943112B2
公开(公告)日：2005-09-13
申请号：US10379265
申请日：2003-03-03
申请人： Bulent M. Basol , Cyprian Uzoh
发明人： Bulent M. Basol , Cyprian Uzoh
IPC分类号： H01L21/288 , H01L21/321 , H01L21/768 , H01L21/44
CPC分类号： C25D17/001 , C25D7/123 , H01L21/2885 , H01L21/32125 , H01L21/7684 , H01L21/76877
摘要： The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.
摘要翻译：本发明的方法在半导体晶片表面中形成铜互连。在该过程中，最初，在晶片的顶表面中提供窄且大的特征，然后通过使用电化学沉积工艺沉积初级铜层。初级铜层完全填满了特征，并在狭窄的特征上形成一个平坦的表面，在大的特征上形成一个非平面的表面。通过采用电化学机械沉积工艺，将二次铜层沉积在初级铜层上，以形成窄和大特征上的平面铜层。在该工艺步骤之后，使用电解抛光工艺来减小平面铜层的厚度。

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