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41. 发明授权

US6147902A High storage capacity non-volatile memory 有权
标题翻译：高存储容量的非易失性存储器
公开(公告)号：US6147902A
公开(公告)日：2000-11-14
申请号：US320315
申请日：1999-05-26
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/02 , G11C11/00 , G11C11/56 , G11C16/04
CPC分类号： G11C11/005 , G11C11/5621 , G11C11/5642 , G11C2211/5641
摘要： A memory device has an array of memory cells, including at least one memory block including multiple-level memory cells adapted for storing each one N.gtoreq.2 bits of information. The at least one memory block also includes electrically erasable and programmable bilevel memory cells, each for storing one bit of information. A circuit is provided for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals supplied to the memory device.
摘要翻译：存储器件具有存储器单元阵列，包括至少一个存储器块，其包括适于存储信息的每个N个/ = 2位的多级存储器单元。所述至少一个存储器块还包括电可擦除和可编程的双层存储器单元，每个用于存储一位信息。提供电路，用于根据提供给存储器件的地址信号来访问和读取所述多级存储器单元之一或同时访问和读取所述电可擦除和可编程双电平存储器单元的N。

42. 发明授权

US6101127A Operating voltage selection circuit for non-volatile semiconductor memories 有权
标题翻译：用于非易失性半导体存储器的工作电压选择电路
公开(公告)号：US6101127A
公开(公告)日：2000-08-08
申请号：US229474
申请日：1999-01-13
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C5/14 , G11C7/10 , G11C16/20 , G11C16/30 , G11C16/06
CPC分类号： G11C16/30 , G11C16/20 , G11C5/14 , G11C7/1045 , G11C2207/2227
摘要： An operating voltage selection circuit for non-volatile semiconductor memories, comprising: means (1) for reading at least one one-time programmable non-volatile memory cell (10), suitable to generate a signal (LV) which indicates the requested type of operating voltage of a non-volatile memory, which depends on the programmed or non-programmed state of the memory cell; memory enabling means (5), which comprise an inverter (30, 31) and are provided with means (32) for modifying the switching threshold of the inverter as a function of the signal that indicates the requested type of operating voltage; output means (2), which are connected to means for sensing data of the memory and to output terminals of the memory, comprising a CMOS inverter (20, 50) and means (23) for modifying the output current of the inverter as a function of the signal (LV) for indicating the requested type of operating voltage; and means (8) for the internal synchronization of the memory, which comprise pluralities of transistors (40, 41, 42) connected in a series/parallel configuration which is determined by the signal (LV) for indicating the requested type of operating voltage, in order to generate signals (CK1, CK2, CK3) for the internal synchronization of the memory.
摘要翻译：一种用于非易失性半导体存储器的工作电压选择电路，包括：用于读取至少一个一次性可编程非易失性存储单元（10）的装置（1），适于生成指示所请求类型的信号（LV）取决于存储器单元的编程或非编程状态的非易失性存储器的工作电压; 存储器使能装置（5），其包括逆变器（30,31），并且设置有用于根据指示所请求的工作电压类型的信号来修改逆变器的开关阈值的装置（32）输出装置（2），其连接到用于感测存储器的数据和存储器的输出端的装置，包括CMOS反相器（20,50）和用于修改逆变器的输出电流作为功能的装置（23）用于指示所请求的工作电压类型的信号（LV）; 以及用于存储器的内部同步的装置（8），其包括由串联/并联配置连接的多个晶体管（40,41,42），所述晶体管由用于指示所请求的工作电压类型的信号（LV）确定，以便产生用于存储器的内部同步的信号（CK1，CK2，CK3）。

43. 发明授权

US5923975A Fabrication of natural transistors in a nonvolatile memory process 失效
标题翻译：在非易失性存储器工艺中制造天然晶体管
公开(公告)号：US5923975A
公开(公告)日：1999-07-13
申请号：US784967
申请日：1997-01-16
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/11517 , H01L27/11543 , H01L27/105
摘要： In a fabrication process of a nonvolatile memory device, natural or low threshold transistors usable in the peripheral circuitry are economically fabricated by exploiting the MATRIX mask that is commonly used for patterning the interpoly dielectric layer for defining the channel length of the natural transistors by patterning the interpoly dielectric layer also over the channel area of the natural transistor, outside the matrix area. The so predefined interpoly dielectric is thereafter exploited as a mask of the polysilicon of a first level during the patterning step of the polysilicon of a second level. Electrical continuity between the polysilicon of the second level and the so patterned gate of polysilicon of the first level are established over the field oxide adjacent to the active area of the natural transistor.
摘要翻译：在非易失性存储器件的制造工艺中，可以在外围电路中使用的天然或低阈值晶体管经济地制造，通过利用通常用于构图多层电介质层的MATRIX掩模，以通过图案化形成天线晶体管的沟道长度也可以在天线晶体管的沟道区域之外的基底区域之外的多层介电层。此后，在第二级的多晶硅的图形化步骤期间，将如此预定的多晶硅电介质用作第一电平的多晶硅的掩模。在与天然晶体管的有源区相邻的场氧化物上建立第二电平的多晶硅与第一电平的多晶硅的图案化栅极之间的电连续性。

44. 发明授权

US5859795A Multi-level memory circuits and corresponding reading and writing methods 失效
标题翻译：多级存储电路及相应的读写方式
公开(公告)号：US5859795A
公开(公告)日：1999-01-12
申请号：US791348
申请日：1997-01-30
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C11/41 , G06F12/16 , G11C11/56 , G11C7/00
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C2211/5641 , G11C29/00
摘要： The present invention relates to a memory circuit of the multi-level type, i.e. a memory circuit having a plurality of memory elements, each adapted to store more than one binary information unit, wherein the memory elements are utilized for storing a number of binary information units tied to an acceptable error rate for a particular application: typically, one bit where a low error rate is sought, and two bits where a higher error rate can be accepted.
摘要翻译：本发明涉及多电平型存储器电路，即具有多个存储器元件的存储器电路，每个存储器电路适于存储多于一个二进制信息单元，其中存储元件用于存储多个二进制信息绑定到特定应用的可接受错误率的单元：通常，寻求低错误率的一个位和可以接受更高错误率的两个位。

45. 发明授权

US5815437A Data input/output managing device, particularly for a non-volatile memory 失效
标题翻译：数据输入/输出管理设备，特别是用于非易失性存储器
公开(公告)号：US5815437A
公开(公告)日：1998-09-29
申请号：US813171
申请日：1997-03-07
申请人： Luigi Pascucci , Antonio Barcella , Paolo Rolandi , Marco Fontana
发明人： Luigi Pascucci , Antonio Barcella , Paolo Rolandi , Marco Fontana
IPC分类号： G11C17/00 , G11C7/10 , G11C16/02 , G11C16/06 , G11C29/00 , G11C11/34 , G11C7/00
CPC分类号： G11C29/70 , G11C7/10
摘要： A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells. The managing device comprises: at least one bidirectional internal bus for the transfer of data from and to the memory; a redundancy management line that is associated with the internal bus; means for enabling/disabling the transmission, over the internal bus, of the data from the memory toward the outside; means for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means for enabling/disabling the connection between the outside of the memory and the redundancy line during the reading of the memory matrix and during its programming.
摘要翻译：一种数据输入/输出管理装置，特别是包括至少一个存储器单元矩阵的非易失性存储器。管理设备包括：至少一个双向内部总线，用于将数据从存储器传送到存储器; 与内部总线相关联的冗余管理线; 用于启用/禁用内部总线上的数据从存储器向外部的传输的装置; 用于启用/禁用其源不同于存储器矩阵的数据部分访问内部总线的装置，用于传输到存储器矩阵; 以及用于在读取存储器矩阵期间和在其编程期间启用/禁用存储器外部与冗余线之间的连接的装置。

46. 发明授权

US08824205B2 Non-volatile electronic memory device with NAND structure being monolithically integrated on semiconductor 有权
公开(公告)号：US08824205B2
公开(公告)日：2014-09-02
申请号：US11279385
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C5/06 , G11C7/02 , G11C16/04 , G11C16/06 , G11C16/24 , G11C8/14 , G11C8/12 , G11C7/18 , G11C7/12
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

47. 发明授权

US08630115B2 Non-volatile electronic memory device with NAND structure being monolithically integrated on semiconductor 有权
标题翻译：具有NAND结构的非易失性电子存储器件单片集成在半导体上
公开(公告)号：US08630115B2
公开(公告)日：2014-01-14
申请号：US13198978
申请日：2011-08-05
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/24 , G11C16/08 , G11C16/06 , G11C16/04 , G11C5/06 , G11C7/02
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
摘要翻译：非易失性电子存储器件被集成在半导体上，并且是具有NAND架构的闪存EEPROM类型，其包括至少一个分为物理扇区的存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列，或者位线的存储单元。给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端行指向源行的相同选择行。

48. 发明申请

US20120005411A1 NON-VOLATILE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY 有权
标题翻译：用于串行非易失性存储器的非易失性配置
公开(公告)号：US20120005411A1
公开(公告)日：2012-01-05
申请号：US13143075
申请日：2008-12-30
申请人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Anddreoli
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Anddreoli
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F9/44573 , G06F2212/72 , G11C16/10 , G11C16/20
摘要： Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置串行非易失性存储器设备的示例性实施例可以包括用于存储从处理器接收的配置值的非易失性配置寄存器，该配置值指定存储器访问操作的一个或多个属性。至少部分地响应于施加到存储器件的功率来读取配置值。

49. 发明申请

US20110286269A1 Non-Volatile Electronic Memory Device With NAND Structure Being Monolithically Integrated On Semiconductor 有权
标题翻译：具有NAND结构的非易失性电子存储器件集成在半导体上
公开(公告)号：US20110286269A1
公开(公告)日：2011-11-24
申请号：US13198978
申请日：2011-08-05
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/08 , H01S4/00
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
摘要翻译：非易失性电子存储器件被集成在半导体上，并且是具有NAND架构的闪存EEPROM类型，其包括至少一个分为物理扇区的存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列，或者位线的存储单元。给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端行指向源行的相同选择行。

50. 发明授权

US07885123B2 Integrated circuit for memory card and memory card using the circuit 有权
标题翻译：用于存储卡和存储卡的集成电路使用该电路
公开(公告)号：US07885123B2
公开(公告)日：2011-02-08
申请号：US09881581
申请日：2001-06-14
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06 , G11C16/18 , G11C8/12
CPC分类号： G11C16/102 , G11C7/16 , G11C16/18
摘要： An integrated circuit for storing data, and for application in a memory card that operates in cooperation with at least one of an external acquisition system and an external processing system includes input/output terminals for receiving the data to be stored, and an electrically programmable non-volatile memory for storing the data in digital format. The memory includes a first terminal for receiving a programming signal for enabling storage of the data, and a second terminal for receiving a reading signal for enabling output of the stored data via the input/output terminals. A memory control circuit is connected to the first and second terminals of the electrically programmable non-volatile memory, and to the input/output terminals for generating programming and reading signals based upon the command signal. The electrically programmable non-volatile memory is erasable by electromagnetic radiation for permitting a non-electrical erasure of the stored data.
摘要翻译：一种用于存储数据并用于应用于与外部采集系统和外部处理系统中的至少一个协同操作的存储卡的集成电路，包括用于接收要存储的数据的输入/输出端子，用于以数字格式存储数据的非易失性存储器。存储器包括用于接收用于使数据存储的编程信号的第一端子，以及用于接收经由输入/输出端子输出存储的数据的读取信号的第二端子。存储器控制电路连接到电可编程非易失性存储器的第一和第二端子以及输入/输出端子，用于基于该命令信号产生编程和读取信号。电可编程非易失性存储器可通过电磁辐射进行擦除，以允许存储数据的非电擦除。

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