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41. 发明申请

US20120147901A1 COMPACTED BINARY IDENTIFIER GENERATION 审中-公开
标题翻译：压缩二进制识别器生成
公开(公告)号：US20120147901A1
公开(公告)日：2012-06-14
申请号：US13325553
申请日：2011-12-14
申请人： Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H04L12/00 , H04J3/00
CPC分类号： H04L69/22 , H04L61/6059 , H04L61/6072
摘要： A technique for generating a compacted binary identifier includes breaking an original binary identifier into equal parts. Each bit of a first one of the parts is exclusive ORed with a start-up value to generate a first result. Each bit of the first result is exclusive ORed with a respective bit of a second one of the parts to generate a second result.
摘要翻译：用于生成压缩二进制标识符的技术包括将原始二进制标识符分解成相等的部分。第一部分的每一位都与启动值进行异或运算以产生第一个结果。第一结果的每一位与该部分的第二个的相应位进行异或运算以产生第二结果。

42. 发明授权

US08681819B2 Programmable multifield parser packet 失效
标题翻译：可编程多字段解析器包
公开(公告)号：US08681819B2
公开(公告)日：2014-03-25
申请号：US13017963
申请日：2011-01-31
申请人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Jan van Lunteren , Fabrice Verplanken
发明人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Jan van Lunteren , Fabrice Verplanken
IPC分类号： G01R31/08 , H04J3/24
CPC分类号： H04L69/22
摘要： A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.
摘要翻译：一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小）由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。

43. 发明授权

US6144637A Data communications 失效
标题翻译：数据通信
公开(公告)号：US6144637A
公开(公告)日：2000-11-07
申请号：US991911
申请日：1997-12-16
申请人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
发明人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
IPC分类号： H04L12/70 , H04Q11/04 , H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译：描述了用于分组数据通信网络（诸如异步传输模式（ATM））网络的流量整形装置。该装置包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。每个传入的数据包被引导到适当的队列。多个定时电路中的每一个在一系列频率中以不同的频率工作。选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

44. 发明申请

US20120198213A1 PACKET HANDLER INCLUDING PLURALITY OF PARALLEL ACTION MACHINES 审中-公开
标题翻译：包装处理器，包括平行动作机械的多样性
公开(公告)号：US20120198213A1
公开(公告)日：2012-08-02
申请号：US13017949
申请日：2011-01-31
申请人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Fabrice Verplanken
发明人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Fabrice Verplanken
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3016 , G06F9/3889
摘要： A packet handler for a packet processing system includes a plurality of parallel action machines, each of the plurality of parallel action machines being configured to perform a respective packet processing function; and a plurality of action machine input registers, wherein each of the plurality of parallel action machines is associated with one or more of the plurality of action machine input registers, and wherein an action machine of the plurality of parallel action machines is automatically triggered to perform its respective packet processing function in the event that data sufficient to perform the actions machine's respective packet processing function is written into the action machine's one or more respective action machine input registers.
摘要翻译：用于分组处理系统的分组处理器包括多个并行动作机器，所述多个并行动作机器中的每一个被配置为执行相应的分组处理功能; 以及多个动作机械输入寄存器，其中，所述多个并行动作机器中的每一个与所述多个动作机械输入寄存器中的一个或多个相关联，并且其中，所述多个并行动作机器的动作机器被自动触发以执行在足以执行动作机器相应的分组处理功能的数据被写入动作机器的一个或多个相应动作机器输入寄存器的情况下，其各自的分组处理功能。

45. 发明授权

US5768273A Method and apparatus for priority level queueing in processing ATM cell header and payload 失效
标题翻译：处理ATM信元头和有效载荷的优先级排队的方法和装置
公开(公告)号：US5768273A
公开(公告)日：1998-06-16
申请号：US547828
申请日：1995-11-01
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： H04L12/931 , H04L12/935 , H04J3/22
CPC分类号： H04L49/30 , H04L49/205 , H04L49/3009
摘要： An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.
摘要翻译： ATM交换机包括具有输入端口和/或输出端口的一个或多个适配器，以及用于将在输入端口处接收的异步传输模式（ATM）单元切换到输出端口的交换结构。为了保持交换机吞吐量，小区被分类为实时（高优先级）或非实时（较低优先级）小区。使用第一组信元处理逻辑以至少等于在输入端口上接收信元的速率的速率处理高优先级信元。仅当不处理高优先级单元时，才使用第二组单元处理逻辑来处理低优先级单元。

46. 发明授权

US5684797A ATM cell multicasting method and apparatus 失效
标题翻译： ATM信元多播方法及装置
公开(公告)号：US5684797A
公开(公告)日：1997-11-04
申请号：US548030
申请日：1995-10-25
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： H04L12/18 , H04L12/931 , H04L12/935 , H04L12/56
CPC分类号： H04L49/201 , H04L49/30
摘要： A multicasting apparatus and method for an Asynchronous Transfer Mode (ATM) switch is described, which uses a single target port (TP) vector attached to each outgoing ATM cell. The target port vector contains identifiers of each port to which the cell has to be transmitted. After transmission of the cell, the identifier relating to respective target port is erased from the TP vector. Hence the TP vector contains only identifiers of target port to which the cell has not yet been transmitted. When the TP vector contains no identifiers, the storage location at which the ATM cell is stored during the transmission, is freed for another cell. Unicast and multicast traffic are treated identically.
摘要翻译：描述了用于异步传输模式（ATM）交换机的多播设备和方法，其使用附接到每个输出ATM信元的单个目标端口（TP）向量。目标端口向量包含单元必须发送到的每个端口的标识符。在小区的传输之后，从TP向量中删除与各目标端口有关的标识符。因此，TP向量仅包含小区尚未被发送到的目标端口的标识符。当TP向量不包含标识符时，传输期间存储ATM信元的存储位置被释放用于另一小区。单播和多播流量处理相同。

47. 发明授权

US5557266A System for cascading data switches in a communication node 失效
标题翻译：用于在通信节点中级联数据交换机的系统
公开(公告)号：US5557266A
公开(公告)日：1996-09-17
申请号：US206363
申请日：1994-03-07
申请人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
发明人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
IPC分类号： H04L12/933 , H04L12/935 , H04L12/937 , H04L29/00 , H03K17/00
CPC分类号： H04L49/15 , H04L29/00 , H04L49/103 , H04L49/254 , H04L49/3027
摘要： A system for cascading data switches in a communication node allows for transfer of data among a plurality of adapters (30-i), expanding a moderate low cost switch 31-1 with additional hardware (31-2, 31-3, 31-4) to interconnect more adapters. The data transfers are performed by a plurality of Burst Relaying Cascaders (32-i) which connect the plurality of switches (31-i). A similar interface connect each adapter to the switch. A set of address information is used by the system to route the data from the source adapter to the target adapter, allowing navigation among the intermediate switches. Each interface contains a table where the address of every adapter of the whole system could be constructed dynamically at each communication node configuration.
摘要翻译：用于在通信节点中级联数据交换的系统允许在多个适配器（30-i）之间传输数据，用附加硬件（31-2,31-3-3,34-4）扩展适度的低成本开关31-1 ）来互连更多适配器。数据传送由连接多个开关（31-i）的多个突发中继级联（32-i）执行。类似的接口将每个适配器连接到交换机。系统使用一组地址信息将数据从源适配器路由到目标适配器，允许在中间交换机之间导航。每个接口包含一个表，其中可以在每个通信节点配置下动态构建整个系统的每个适配器的地址。

48. 发明申请

US20120147892A1 ANALYSIS OF NETWORK PACKETS USING A GENERATED HASH CODE 审中-公开
标题翻译：使用生成的哈希码对网络分组进行分析
公开(公告)号：US20120147892A1
公开(公告)日：2012-06-14
申请号：US13325597
申请日：2011-12-14
申请人： Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L45/74 , H04L69/22
摘要： A technique for analyzing network packets includes receiving, by a network processor, a network packet having a packet header including address and control information. A set of bytes are extracted, using the network processor, from the packet header and a set of input bits for generating a hash code are derived, using the network processor, from the set of bytes. Finally, the hash code is generated using the input bits.
摘要翻译：用于分析网络分组的技术包括由网络处理器接收具有包含地址和控制信息的分组报头的网络分组。使用网络处理器从分组报头提取一组字节，并且使用网络处理器从该组字节导出用于生成散列码的一组输入比特。最后，使用输入位生成哈希码。

49. 发明申请

US20120300630A1 IDENTIFICATION OF QOS CLASSIFICATION BASED ON PACKET ATTRIBUTES 有权
标题翻译：基于分组属性的QOS分类识别
公开(公告)号：US20120300630A1
公开(公告)日：2012-11-29
申请号：US13302489
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
IPC分类号： H04L12/24
CPC分类号： H04L47/2441 , H04L69/22
摘要： A method, a system, and a computer program product is disclosed for identifying a quality of service (QoS) classification of a packet in a network by a network processor. The method comprising: providing a table wherein a priority value with a maximum of N values is used as an index into the table to retrieve a QoS classification having a maximum of M values with M less than N; receiving a data packet in a stream of data packets; extracting at least two priority indicator values from the packet; converting the at least two priority indicator values into a priority value; utilizing the priority value as an index into the table; extracting the entry in the table corresponding to the priority value as the QoS classification of the packet; and utilizing the QoS classification for subsequent processing of the data packet.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于通过网络处理器来识别网络中的分组的服务质量（QoS）分类。该方法包括：提供一个表，其中将具有最大N个值的优先级值用作表中的索引以检索具有M小于N的最大M个值的QoS分类; 在数据包流中接收数据包; 从分组中提取至少两个优先级指示符值; 将所述至少两个优先级指示符值转换为优先级值; 利用优先级值作为表中的索引; 提取对应于优先级值的表中的条目作为分组的QoS分类; 并利用QoS分类来对数据分组进行后续处理。

50. 发明申请

US20070002172A1 LINKING FRAME DATA BY INSERTING QUALIFIERS IN CONTROL BLOCKS 审中-公开
标题翻译：通过在控制块中插入合格者来连接框架数据
公开(公告)号：US20070002172A1
公开(公告)日：2007-01-04
申请号：US11469390
申请日：2006-08-31
申请人： Jean Calvignac , Marco Heddes , Joseph Logan , Fabrice Verplanken
发明人： Jean Calvignac , Marco Heddes , Joseph Logan , Fabrice Verplanken
IPC分类号： H04N11/00
CPC分类号： H04L49/3081 , G06F13/4243 , H04L2012/5681
摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
摘要翻译：一种通过在控制块中插入限定符来减少存储器访问的方法和系统。在一个实施例中，系统包括被配置为处理数据帧的处理器。处理器可以包括多个缓冲器，其被配置为存储数据帧，其中每个数据帧可以与帧控制块相关联。与数据帧相关联的每个帧控制块可以与一个或多个缓冲器控制块相关联。每个控制块，例如帧控制块，缓冲器控制块，可以包括包含与当前控制块无关的信息的一个或多个限定符字段。相反，限定符可以包括与另一个控制块有关的信息。队列中的最后帧控制块以及与帧控制块相关联的最后一个缓冲器控制块可以包括没有信息的字段，从而减少对这些字段中的访问信息的存储器访问。

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