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41. 发明授权

US08461629B2 Semiconductor device and method of fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08461629B2
公开(公告)日：2013-06-11
申请号：US13178755
申请日：2011-07-08
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

42. 发明申请

US20120196434A1 E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit 有权
标题翻译：嵌入式存储器电路的电可编程冗余中的电熔丝结构设计
公开(公告)号：US20120196434A1
公开(公告)日：2012-08-02
申请号：US13443550
申请日：2012-04-10
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L21/02
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

43. 发明授权

US07998830B2 Semiconductor device with both I/O and core components and method of fabricating same 有权
标题翻译：具有I / O和核心部件的半导体器件及其制造方法
公开(公告)号：US07998830B2
公开(公告)日：2011-08-16
申请号：US12961167
申请日：2010-12-06
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

44. 发明授权

US07868386B2 Method and apparatus for semiconductor device with improved source/drain junctions 有权
标题翻译：具有改善的源极/漏极结的半导体器件的方法和装置
公开(公告)号：US07868386B2
公开(公告)日：2011-01-11
申请号：US12058997
申请日：2008-03-31
申请人： Kong-Beng Thei , Chung Long Cheng , Harry Chuang
发明人： Kong-Beng Thei , Chung Long Cheng , Harry Chuang
IPC分类号： H01L23/58 , H01L29/76 , H01L29/94
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L29/105 , H01L29/1083 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.
摘要翻译：公开了一种具有改善的源极/漏极结的半导体器件和用于制造该器件的方法。优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度与45度之间。另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

45. 发明授权

US07868361B2 Semiconductor device with both I/O and core components and method of fabricating same 有权
公开(公告)号：US07868361B2
公开(公告)日：2011-01-11
申请号：US11766425
申请日：2007-06-21
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

46. 发明授权

US07803674B2 Methods for fabricating SOI devices 有权
标题翻译：制造SOI器件的方法
公开(公告)号：US07803674B2
公开(公告)日：2010-09-28
申请号：US12468131
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

47. 发明授权

US09099556B2 Transistor having an active region with wing structure 有权
标题翻译：晶体管具有机翼结构的有源区域
公开(公告)号：US09099556B2
公开(公告)日：2015-08-04
申请号：US13213409
申请日：2011-08-19
申请人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
发明人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
IPC分类号： H01L29/76 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/41775 , H01L29/0653 , H01L29/0692 , H01L29/1033 , H01L29/1045 , H01L29/78 , H01L29/7823 , H01L29/7835
摘要： A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.
摘要翻译：半导体器件包括具有通道区域的有源区域和与栅极介电层下方的沟道区域邻接的至少一个翼区域。所述至少一个机翼区域可以是穿过所述通道区域的两个对称翼区域。

48. 发明授权

US09054025B2 Process for controlling shallow trench isolation step height 有权
标题翻译：控制浅沟槽隔离台阶高度的工艺
公开(公告)号：US09054025B2
公开(公告)日：2015-06-09
申请号：US12478135
申请日：2009-06-04
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
IPC分类号： H01L21/66 , H01L21/762
CPC分类号： H01L22/20 , H01L21/76224 , H01L22/12
摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.
摘要翻译：公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

49. 发明申请

US20120270379A1 METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS 有权
标题翻译：在门窗最后过程中制造多孔门结构的方法
公开(公告)号：US20120270379A1
公开(公告)日：2012-10-25
申请号：US13538220
申请日：2012-06-29
申请人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要： A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译：一种半导体器件制造方法，包括在衬底的第一部分中形成多个栅极结构，其中所述多个栅极结构具有第一高度。第一金属栅极结构形成在衬底的第二部分中，第一金属栅极结构被隔离区包围。在基板的第二部分中形成多个虚拟栅极结构。多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。多个虚拟结构具有与多个栅极结构基本平面的顶表面，并且覆盖基板的第二部分的图案密度的至少5％。

50. 发明申请

US20120146057A1 METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE 有权
标题翻译：在应变半导体器件中制作间隔物的方法
公开(公告)号：US20120146057A1
公开(公告)日：2012-06-14
申请号：US13399394
申请日：2012-02-17
申请人： Chen-Pin Hsu , Kong-Beng Thei , Harry Chuang
发明人： Chen-Pin Hsu , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L29/78 , H01L29/24
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823864 , H01L29/0847 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.
摘要翻译：本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成栅极叠层的侧壁上的栅极间隔物。

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