专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 外观设计

USD661270S1 Television receiver 有权
公开(公告)号：USD661270S1
公开(公告)日：2012-06-05
申请号：US29409971
申请日：2011-12-30
申请人： Hyunbyung Cha , Chul Lee , Myungwhoon Lee , Yoonkyeong Lee , Jongchul Kim
设计人： Hyunbyung Cha , Chul Lee , Myungwhoon Lee , Yoonkyeong Lee , Jongchul Kim

42. 发明申请

US20110095350A1 VERTICAL TYPE INTEGRATED CIRCUIT DEVICES, MEMORY DEVICES, AND METHODS OF FABRICATING THE SAME 有权
标题翻译：垂直型集成电路装置，存储装置及其制造方法
公开(公告)号：US20110095350A1
公开(公告)日：2011-04-28
申请号：US12891910
申请日：2010-09-28
申请人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
发明人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： H01L27/10897 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L29/0657 , H01L29/42356 , H01L29/66666 , H01L29/7827
摘要： A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.
摘要翻译：垂直型集成电路装置包括基板和从基板垂直突出的支柱。支柱包括其中较低的杂质区域和上部杂质区域以及它们之间的垂直沟道区域。包括其中较低杂质区域的柱的一部分包括从其横向延伸的台面。该器件还包括在柱的第一侧壁上延伸并与下部杂质区电接触的第一导电线，以及在邻近垂直沟道区的柱的第二侧壁上延伸的第二导电线。第二导电线在垂直于第一导电线的方向上延伸并且与台面间隔开。还讨论了相关装置和制造方法。

43. 发明授权

US07883972B2 Semiconductor device having a fin structure and method of manufacturing the same 失效
标题翻译：具有翅片结构的半导体器件及其制造方法
公开(公告)号：US07883972B2
公开(公告)日：2011-02-08
申请号：US12219984
申请日：2008-07-31
申请人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
发明人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.
摘要翻译：半导体器件可以包括具有连接在源极/漏极图案之间的源极/漏极区域和沟道鳍片的鳍结构。栅极绝缘层可以设置在通道散热片上。栅电极可以包括下栅极图案和上栅极图案。下栅极图案可以在垂直方向上延伸并接触栅极绝缘层。上栅极图案可以在基本上垂直于第一水平方向的第二水平方向上延伸。上栅极图案可以连接到下栅极图案的上部。

44. 发明授权

US07879703B2 Method of fabricating semiconductor device for reducing thermal burden on impurity regions of peripheral circuit region 失效
标题翻译：制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法
公开(公告)号：US07879703B2
公开(公告)日：2011-02-01
申请号：US12321335
申请日：2009-01-20
申请人： Kyoung-Ho Jung , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Joon-Seok Moon , Cheol-Kyu Lee , Sung-Il Cho
发明人： Kyoung-Ho Jung , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Joon-Seok Moon , Cheol-Kyu Lee , Sung-Il Cho
IPC分类号： H01L21/425
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/82385
摘要： A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.
摘要翻译：制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。可以在电池活性区域中形成第一电池杂质区域。可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。牺牲绝缘层可以与外围栅极图案相邻地去除。第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。

45. 发明申请

US20100299513A1 MEMORY APPARATUS AND METHOD THEREFOR 有权
标题翻译：记忆装置及其方法
公开(公告)号：US20100299513A1
公开(公告)日：2010-11-25
申请号：US12771203
申请日：2010-04-30
申请人： Seung-woo RYU , Jae-min Ryu , Chul Lee
发明人： Seung-woo RYU , Jae-min Ryu , Chul Lee
IPC分类号： G06F15/177 , G06F12/02 , G06F12/00
CPC分类号： G06F3/0679 , G06F11/1441 , G06F13/1694
摘要： A memory apparatus and an operation of the memory apparatus which allow quick booting are provided. The memory apparatus includes a volatile memory, a non-volatile memory, and a memory control unit to control input/output of data stored in the volatile memory and the non-volatile memory. The memory control unit restores data, according to a control command input from outside of the memory apparatus, from the non-volatile memory to the volatile memory in an on-demand fashion during booting.
摘要翻译：提供了允许快速启动的存储装置和存储装置的操作。存储装置包括易失性存储器，非易失性存储器和存储器控制单元，用于控制存储在易失性存储器和非易失性存储器中的数据的输入/输出。存储器控制单元根据从存储装置外部输入的控制命令，在引导期间按照需要将数据从非易失性存储器恢复到易失性存储器。

46. 发明授权

US07521766B2 Transistor and method of forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US07521766B2
公开(公告)日：2009-04-21
申请号：US11070598
申请日：2005-03-01
申请人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
发明人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
摘要翻译：根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。活性结构包括在源极/漏极区域下形成阻挡区的沟槽。栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

47. 发明授权

US07407845B2 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07407845B2
公开(公告)日：2008-08-05
申请号：US11048369
申请日：2005-01-31
申请人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
发明人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/785 , H01L29/7854 , H01L29/78603 , H01L29/78648
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.
摘要翻译：在一个实施例中，半导体器件包括具有下层和覆盖在下层上的上层的半导体衬底。上层被布置和构造成形成彼此间隔开并从下层的上表面突出的第一和第二有源区。桥接形状的第三有源区域与下层的上表面垂直地间隔开并且连接第一和第二有源区域。该器件还包括栅电极，其形成有围绕第三有源区的栅绝缘层，使得第三有源区用作沟道。

48. 发明授权

US07317230B2 Fin FET structure 有权
标题翻译：翅片FET结构
公开(公告)号：US07317230B2
公开(公告)日：2008-01-08
申请号：US11041063
申请日：2005-01-21
申请人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
发明人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7854
摘要： A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.
摘要翻译：鳍式FET结构采用负字线方案。翅片FET的栅极采用掺杂有n +杂质的电极，不执行用于阈值电压控制的沟道掺杂，或者通过低密度执行沟道掺杂，从而显着提高了鳍式FET的特性。半导体衬底形成为第一导电类型，并且第一导电类型的鳍有源区域从半导体衬底的上表面突出并连接到半导体衬底。在半导体衬底上形成绝缘层，并且在翅片有源区的上部和侧壁形成栅极绝缘层。在绝缘层和栅极绝缘层上形成栅电极。源极和漏极形成在栅极两侧的鳍片有源区域中。

49. 发明申请

US20070042582A1 Method of forming a nanowire and method of manufacturing a semiconductor device using the same 有权
标题翻译：形成纳米线的方法和使用该纳米线的半导体器件的制造方法
公开(公告)号：US20070042582A1
公开(公告)日：2007-02-22
申请号：US11431216
申请日：2006-05-10
申请人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
发明人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/465
CPC分类号： H01L21/3083 , B82Y10/00 , B82Y30/00 , H01L29/0665 , H01L29/0673 , Y10S977/938
摘要： In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire is formed, and additionally covers a second region of the substrate connected to the first region. An opening is formed by etching an exposed portion of the substrate by the insulation layer pattern. A spacer is formed on sidewalls of the opening and the insulation layer pattern. The nanowire connected to the second region is formed by anisotropically etching a portion of the substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.
摘要翻译：在半导体器件中形成纳米线的方法中，通过部分蚀刻体半导体衬底形成沟槽。在衬底上形成绝缘层图案以填充沟槽。绝缘层图案覆盖形成有纳米线的基板的第一区域，并且另外覆盖连接到第一区域的基板的第二区域。通过用绝缘层图案蚀刻衬底的暴露部分形成开口。在开口和绝缘层图案的侧壁上形成间隔物。连接到第二区域的纳米线通过各向异性蚀刻由开口暴露的基板的一部分，直到形成在沟槽中的绝缘层图案的一部分露出来形成。

50. 发明申请

US20060267879A1 ELECTRON EMISSION DISPLAY AND DRIVING METHOD THEREOF 审中-公开
标题翻译：电子发射显示及其驱动方法
公开(公告)号：US20060267879A1
公开(公告)日：2006-11-30
申请号：US11383875
申请日：2006-05-17
申请人： Chul Lee
发明人： Chul Lee
IPC分类号： G09G3/22
CPC分类号： G09G3/22 , G09G2310/0267 , G09G2330/02 , G09G2330/04
摘要： A scan driver or a power supply in an electron emission display may be controlled to protect the electron emission display when a pulse of a scan signal pauses in an on signal state for a predetermined period.
摘要翻译：可以控制电子发射显示器中的扫描驱动器或电源，以在扫描信号的脉冲在接通信号状态下暂停预定时间段时保护电子发射显示。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式