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41. 发明申请

US20080266098A1 RFID READERS CO-EXISTING WITH OTHER ISM-BAND DEVICES 审中-公开
标题翻译： RFID读写器与其他ISM-BAND设备并存
公开(公告)号：US20080266098A1
公开(公告)日：2008-10-30
申请号：US12056120
申请日：2008-03-26
申请人： Ali Aiouaz , Christopher J. Diorio , Aanand Esterberg , Harsh Jain , Omar Khwaja , David Ord , Mike Thomas
发明人： Ali Aiouaz , Christopher J. Diorio , Aanand Esterberg , Harsh Jain , Omar Khwaja , David Ord , Mike Thomas
IPC分类号： H04B7/00
CPC分类号： H04W52/16 , H04W52/245 , H04W52/246 , H04W52/247
摘要： Radio Frequency IDentification (RFID) reader system, software, and methods are provided, such that an operational processing block for the RFID reader to communicate with an RFID tag uses a RF spectrum portion subdivided into a set of channels. The communication takes place in the presence of a foreign device that uses a subset of first channels of the RF spectrum and does not use a subset of second channels of the spectrum. The methods cause a radiating power directed towards the tag to be reduced and a radiating dwell time to be changed. This is to assure that co-existing systems can operate without compromising their functionality and operational quality. In some embodiments, the radiating power is reduced to zero.
摘要翻译：提供射频识别（RFID）读取器系统，软件和方法，使得用于RFID读取器与RFID标签通信的操作处理块使用被划分成一组通道的RF频谱部分。通信在存在使用RF频谱的第一信道的子集并且不使用频谱的第二信道的子集的外部设备的存在下进行。这些方法会导致朝向标签的辐射功率减小，并且改变辐射停留时间。这是为了确保共存系统可以在不影响其功能和操作质量的情况下运行。在一些实施例中，辐射功率被减小到零。

42. 发明授权

US07408466B2 Adjusting RFID waveform shape in view of detected RF energy 有权
标题翻译：鉴于检测到的RF能量调整RFID波形形状
公开(公告)号：US07408466B2
公开(公告)日：2008-08-05
申请号：US11412170
申请日：2006-04-25
申请人： Christopher J. Diorio , Kurt E. Sundstrom , Todd E. Humes , Paul Dietrich
发明人： Christopher J. Diorio , Kurt E. Sundstrom , Todd E. Humes , Paul Dietrich
IPC分类号： G08B13/14
CPC分类号： G06K7/0008
摘要： Systems, software, devices, and methods are described for an RFID reader system to communicate with RFID tags. RF energy encountered in conjunction with using a selected channel is detected and used to adjust a waveform shaping parameter. RF waves can be transmitted from the reader to the RFID tags and RF waves can be backscattered from the RFID tags. At least some of the RF waves transmitted to or backscattered from the RFID tags have a waveform with a shape according to the adjusted waveform shaping parameter.
摘要翻译：描述了RFID读取器系统与RFID标签通信的系统，软件，设备和方法。检测并结合使用所选择的信道遇到的RF能量来调整波形整形参数。 RF波可以从读取器发送到RFID标签，并且RF波可以从RFID标签反向散射。从RFID标签发射或反向散射的至少一些RF波具有根据经调整的波形整形参数的形状的波形。

43. 发明授权

US07388420B2 Rewriteable electronic fuses 有权
标题翻译：可重写电子保险丝
公开(公告)号：US07388420B2
公开(公告)日：2008-06-17
申请号：US10814866
申请日：2004-03-30
申请人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
发明人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
IPC分类号： H01H37/76
CPC分类号： G11C16/0441 , G11C7/20 , G11C14/00 , G11C16/045
摘要： Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.
摘要翻译：可重写电子熔丝包括耦合到一个或多个非易失性存储元件的锁存器和/或逻辑门。非易失性存储器元件被配置为被编程为能够使相关联的电子电路稳定到预定状态的存储器值，因为上电或复位信号被施加到保险丝。虽然不是必需的，但是在可重写电子熔丝中使用的非易失性存储元件可以包括浮栅晶体管。存储在给定浮栅晶体管的浮置栅极上的电荷量确定存储器值，并且因此确定保险丝上电或复位时保险丝熔断的状态。

44. 发明授权

US07242614B2 Rewriteable electronic fuses 有权
公开(公告)号：US07242614B2
公开(公告)日：2007-07-10
申请号：US10813907
申请日：2004-03-30
申请人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
发明人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
IPC分类号： G11C11/34 , G11C17/18
CPC分类号： G11C16/0441 , G11C14/00 , G11C16/045 , H01L27/105 , H01L27/115 , H01L29/7883 , H03K3/02335
摘要： Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

45. 发明授权

US07071507B2 High-voltage CMOS-compatible capacitors 有权
标题翻译：高压CMOS兼容电容
公开(公告)号：US07071507B2
公开(公告)日：2006-07-04
申请号：US10931583
申请日：2004-09-01
申请人： Christopher J. Diorio , Frederic J. Bernard
发明人： Christopher J. Diorio , Frederic J. Bernard
IPC分类号： H01L27/108
CPC分类号： H01L27/0811 , H01L27/0805 , H01L29/788
摘要： A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate comprising a first semiconductive body and a second plate comprising a floating electrode. The first and second semiconductive bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.
摘要翻译：高电压堆叠电容器包括第一电容器和第二电容器。每个电容器包括包括第一半导电体的第一板和包括浮动电极的第二板。第一和第二半导电体彼此电隔离。浮置电极包括被配置为自适应到小于施加在堆叠电容器上的工作电压的值的电容间节点。

46. 发明授权

US07042701B2 High-voltage CMOS-compatible capacitors 有权
公开(公告)号：US07042701B2
公开(公告)日：2006-05-09
申请号：US10931582
申请日：2004-09-01
申请人： Christopher J. Diorio , Frederic J. Bernard
发明人： Christopher J. Diorio , Frederic J. Bernard
IPC分类号： H01G4/30
CPC分类号： H01L27/0811 , H01L27/0805 , H01L29/788
摘要： A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.

47. 发明授权

US06853583B2 Method and apparatus for preventing overtunneling in pFET-based nonvolatile memory cells 有权
标题翻译：用于防止基于pFET的非易失性存储单元中的过度隧穿的方法和装置
公开(公告)号：US06853583B2
公开(公告)日：2005-02-08
申请号：US10245183
申请日：2002-09-16
申请人： Christopher J. Diorio , Chad Lindhorst , Shail Srinivas , Alberto Pesavento , Troy Gilliland
发明人： Christopher J. Diorio , Chad Lindhorst , Shail Srinivas , Alberto Pesavento , Troy Gilliland
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3477 , G11C16/3404 , G11C16/3468 , G11C16/3472
摘要： Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.
摘要翻译：方法和装置可以防止基于pFET的非易失性浮动栅极存储器（NVM）单元中的超导。在其中从基于pFET的NVM单元的浮置栅极去除电荷载流子的隧穿过程中，监测存储单元晶体管的沟道电流，并将其与在注入中维持导通通道所需的预定最小沟道电流进行比较晶体管的存储单元。当监测的通道电流下降到预定的最小通道电流以下时，电荷载流子通过冲击电离热电子注入（IHEI）注入到浮动栅极上，从而避免了超导。

48. 发明授权

US06842327B1 High-voltage CMOS-compatible capacitors 有权
公开(公告)号：US06842327B1
公开(公告)日：2005-01-11
申请号：US10635247
申请日：2003-08-05
申请人： Christopher J. Diorio , Frederic J. Bernard
发明人： Christopher J. Diorio , Frederic J. Bernard
IPC分类号： H01L27/08 , H01G4/30
CPC分类号： H01L27/0811 , H01L27/0805 , H01L29/788
摘要： A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate comprising a first semiconductive body and a second plate comprising a floating electrode. The first and second semiconductor bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.

49. 发明授权

US6144581A pMOS EEPROM non-volatile data storage 有权
标题翻译： pMOS EEPROM非易失性数据存储
公开(公告)号：US6144581A
公开(公告)日：2000-11-07
申请号：US201327
申请日：1998-11-30
申请人： Christopher J. Diorio , Carver A. Mead
发明人： Christopher J. Diorio , Carver A. Mead
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/10
摘要： A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.
摘要翻译： pMOS EEPROM单元包括源极，漏极，通道，控制栅极和阱接触。该器件是一个功能齐全的单元件p型浮栅MOSFET。浮动栅极与阱接触重叠，并完全围绕漏极和源植入。通过热电子注入将pMOS单元写入，使用内在反馈机制来写入模拟值。通过在晶体管漏极处的空穴冲击电离在通道中产生热电子。 Fowler-Nordheim隧道消除了pMOS细胞。隧道电压仅施加到阱以从浮动栅极隧道电子。井源井漏井路口通过护环免受破坏。

50. 发明授权

US5825063A Three-terminal silicon synaptic device 失效
标题翻译：三端硅突触装置
公开(公告)号：US5825063A
公开(公告)日：1998-10-20
申请号：US690198
申请日：1996-07-26
申请人： Christopher J. Diorio , Paul E. Hasler , Bradley A. Minch , Carver A. Mead
发明人： Christopher J. Diorio , Paul E. Hasler , Bradley A. Minch , Carver A. Mead
IPC分类号： G11C27/00 , H01L29/788
CPC分类号： G11C27/005 , H01L29/7885
摘要： A three-terminal silicon MOS transistor with a time-varying transfer function is provided which may operate both as a single transistor analog learning device and as a single transistor non-volatile analog memory. The time-varying transfer function is achieved by adding or removing electrons from the fully insulated floating gate of an N-type MOS floating gate transistor. The transistor has a control gate capacitively coupled to the floating gate; it is from the perspective of this control gate that the transfer function of the transistor is modified. Electrons are removed from the floating gate via Fowler-Nordheim tunneling. Electrons are added to the floating gate via hot-electron injection.
摘要翻译：提供具有时变传递函数的三端硅MOS晶体管，其可以同时作为单晶体管模拟学习装置和单晶体管非易失性模拟存储器工作。通过从N型MOS浮栅晶体管的完全绝缘的浮栅中添加或去除电子来实现时变传递函数。晶体管具有电容耦合到浮动栅极的控制栅极; 从该控制栅极的角度看，晶体管的传递函数被修改。电子通过Fowler-Nordheim隧道从浮动门去除。电子通过热电子注入添加到浮动栅极。

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