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41. 发明授权

US5541876A Memory cell fabricated by floating gate structure 失效
标题翻译：通过浮栅结构制造的存储单元
公开(公告)号：US5541876A
公开(公告)日：1996-07-30
申请号：US251972
申请日：1994-06-01
申请人： Chen-Chin Hsue , Ming-Tzong Yang , Chung-Cheng Wu
发明人： Chen-Chin Hsue , Ming-Tzong Yang , Chung-Cheng Wu
IPC分类号： G11C17/12 , H01L27/112 , G11C11/34
CPC分类号： G11C17/12 , H01L27/112
摘要： A memory cell and a process for making it are disclosed. The ROM code is not implanted in the floating gate for cells selected to be "off". This memory cell has a much lower threshold voltage than conventional cells and the implantation induced crystal damage is avoided.
摘要翻译：公开了一种存储单元及其制造方法。对于选择为“关闭”的单元，ROM码不会植入浮动门。该存储单元具有比常规电池低得多的阈值电压，并且避免了注入诱导的晶体损伤。

42. 发明授权

US5510214A Double destruction phase shift mask 失效
标题翻译：双重破坏相移掩模
公开(公告)号：US5510214A
公开(公告)日：1996-04-23
申请号：US318425
申请日：1994-10-05
申请人： Hong-Tsz Pan , Ming-Tzong Yang
发明人： Hong-Tsz Pan , Ming-Tzong Yang
IPC分类号： G03F1/29 , G03F1/32 , G03F9/00
CPC分类号： G03F1/32 , G03F1/29
摘要： This invention describes the use and methods of fabrication of a double destruction phase shift mask. The double destruction phase shift mask combines transparent phase shifting regions and attenuating phase shifting regions to form interference patterns in light projected through the mask which reduce the light intensity to nearly zero in the regions of the projected light corresponding to pattern elements. This eliminates the ghost line which can occur with conventional phase shifting masks. The double destruction phase shift mask provides improved depth of focus and edge definition.
摘要翻译：本发明描述了制造双重破坏相移掩模的用途和方法。双重破坏相移掩模组合透明相移区域和衰减相移区域，以在通过掩模投射的光中形成干涉图案，其在对应于图案元素的投影光的区域中将光强度降低到接近零。这消除了常规相移掩模可能发生的鬼线。双重破坏相移掩模提供了改进的聚焦深度和边缘定义。

43. 发明授权

US5496200A Sealed vacuum electronic devices 失效
标题翻译：密封真空电子设备
公开(公告)号：US5496200A
公开(公告)日：1996-03-05
申请号：US305560
申请日：1994-09-14
申请人： Ming-Tzong Yang , Hong-Tsz Pan
发明人： Ming-Tzong Yang , Hong-Tsz Pan
IPC分类号： H01J9/02 , H01J1/30
CPC分类号： H01J9/025
摘要： The method is for manufacturing sealed vacuum field emission devices. A field EMITTER TIP is formed on a silicon substrate. A first dielectric layer is formed over the field EMITTER TIP and over the silicon substrate. The first dielectric layer is planarized to provide a smooth top surface co-planar with the top of the field EMITTER TIP. A grid metal layer is formed over the first dielectric layer. A second dielectric layer is formed over the grid metal layer. The second dielectric layer is patterned to provide an opening, vertically located over the field emission device, to the grid metal layer. The grid metal layer is patterned in the area defined by the opening. The first dielectric layer is removed in the region defined by the opening, and also a portion of the first dielectric layer under the grid metal layer. The upper portion of the opening is narrowed. A second metal layer is formed over the second dielectric layer and over the opening, in a vacuum environment, such that the field EMITTER TIP is in a sealed vacuum.
摘要翻译：该方法用于制造密封的真空场发射装置。在硅衬底上形成场发射极TIP。第一电介质层形成在场发射极TIP上方和硅衬底上。第一介电层被平坦化以提供与场发射器提示的顶部共面的光滑顶表面。栅极金属层形成在第一介电层上。在栅格金属层上形成第二介电层。图案化第二电介质层以提供垂直位于场发射器件上方的开口到栅格金属层。栅格金属层在由开口限定的区域中被图案化。在由开口限定的区域中以及在栅格金属层下方的第一电介质层的一部分去除第一电介质层。开口的上部变窄。第二金属层在真空环境中形成在第二电介质层上方和开口上方，使得场发射器提示处于密封真空中。

44. 发明授权

US5438009A Method of fabrication of MOSFET device with buried bit line 失效
标题翻译：具有掩埋位线的MOSFET器件的制造方法
公开(公告)号：US5438009A
公开(公告)日：1995-08-01
申请号：US100307
申请日：1993-04-02
申请人： Ming-Tzong Yang , Gary Hong
发明人： Ming-Tzong Yang , Gary Hong
IPC分类号： H01L27/108 , H01L27/00 , H01L21/70
CPC分类号： H01L27/10808
摘要： A doped FET DRAM includes a silicon substrate, with a buried bit line in the silicon substrate. A plug extends down through the substrate to the bit line. A source region and a drain region are positioned above the plug in the substrate with one thereof connected to the plug with a layer of gate oxide above the source region and drain region. A gate above the gate oxide is juxtaposed with the source region and drain region. The source is connected to a capacitor formed of two layers of polysilicon separated by a dielectric of an ONO oxide layer.
摘要翻译：掺杂FET DRAM包括在硅衬底中具有掩埋位线的硅衬底。插头通过衬底向下延伸到位线。源极区域和漏极区域位于衬底上的插塞上方，其中一个源极与源极区域和漏极区域上方连接有栅极氧化物层。栅极氧化物上方的栅极与源区和漏区并列。源极连接到由由ONO氧化物层的电介质隔开的两层多晶硅形成的电容器。

45. 发明授权

US5380673A Dram capacitor structure 失效
标题翻译：戏剧电容器结构
公开(公告)号：US5380673A
公开(公告)日：1995-01-10
申请号：US239130
申请日：1994-05-06
申请人： Ming-Tzong Yang , Chen-Chiu Hsue , Anchor Chen
发明人： Ming-Tzong Yang , Chen-Chiu Hsue , Anchor Chen
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92
摘要： A new structure and method for fabricating a stacked capacitor with increased capacitance and which is more manufacturable was accomplished. The stacked capacitor is part of a dynamic random access memory (DRAM) cell for storing charge on the capacitor and together with a field effect transistor (MOSFET) make up the individual DRAM storage cells on a DRAM chip. Fabricating this improved stacked capacitor involves using an additional electrically conducting layer in the polysilicon layer of the bottom electrode. For example, this layer can be composed from materials in the metal nitride group having high conductivity. One preferred choice being titanium nitride (TiN). The bottom electrode is formed by depositing and patterning a thin layer of polysilicon and a thin layer of the electrically conducting layer and then depositing an upper layer of polysilicon from which vertical sidewalls are formed. The conducting layer provides an etch end point for accurately etching to the correct depth. This provided for a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom electrode and forming a top capacitor electrode to complete the stacked capacitor. The bottom electrode contacts one source/drain contacts of the MOSFET and the bit line contacts the other source/drain contact completing the improved DRAM cell.
摘要翻译：实现了一种用于制造具有增加的电容并且更可制造的层叠电容器的新结构和方法。堆叠电容器是用于在电容器上存储电荷并与场效应晶体管（MOSFET）一起构成DRAM芯片上的各个DRAM存储单元的动态随机存取存储器（DRAM）单元的一部分。制造这种改进的堆叠电容器包括在底部电极的多晶硅层中使用附加的导电层。例如，该层可以由具有高导电性的金属氮化物基团中的材料构成。一种优选的选择是氮化钛（TiN）。底部电极通过沉积和图案化多晶硅薄层和导电层的薄层而形成，然后沉积形成垂直侧壁的多晶硅上层。导电层提供蚀刻终点以准确地蚀刻到正确的深度。这提供了可重复和更可制造的过程。然后通过在底部电极上沉积高介电常数绝缘体层并形成顶部电容器电极以完成堆叠的电容器来完成叠层电容器。底部电极接触MOSFET的一个源极/漏极触点，并且位线接触另一个源极/漏极触点，从而完成改进的DRAM单元。

46. 发明授权

US5306657A Process for forming an FET read only memory device 失效
标题翻译：用于形成FET只读存储器件的工艺
公开(公告)号：US5306657A
公开(公告)日：1994-04-26
申请号：US35182
申请日：1993-03-22
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L21/8246 , H01L21/70
CPC分类号： H01L27/1126
摘要： A method of producing a ROM device wherein parallel spaced bit line regions are formed in a semiconductor substrate, blanket layers of (1) polysilicon, (2) etch stop material, and (3) polysilicon, are deposited, the layers etched to form orthogonal parallel word lines on the surface of the substrate, a thick insulating layer deposited over the word lines, a resist layer deposited, exposed and developed to define a desired code implant pattern, the exposed areas of the thick layer removed, and the underlie upper polysilicon layer of the bit line removed, and ion implanted into the substrate to form a code implant.
摘要翻译：一种制造ROM器件的方法，其中在半导体衬底中形成并行隔开的位线区域，沉积（1）多晶硅，（2）蚀刻停止材料和（3）多晶硅的覆盖层，蚀刻所述层以形成正交在衬底表面上的平行字线，沉积在字线上的厚绝缘层，沉积，暴露和显影以限定所需代码注入图案的抗蚀剂层，去除了厚层的暴露区域，以及上层多晶硅去除位线的层，并将离子注入到衬底中以形成代码植入物。

47. 发明授权

US08921941B2 ESD protection device and method for fabricating the same 有权
标题翻译： ESD保护装置及其制造方法
公开(公告)号：US08921941B2
公开(公告)日：2014-12-30
申请号：US13103112
申请日：2011-05-09
申请人： Ming-Tzong Yang , Ming-Cheng Lee
发明人： Ming-Tzong Yang , Ming-Cheng Lee
IPC分类号： H01L23/62 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/10 , H01L21/8234 , H01L29/786 , H01L27/02 , H01L21/265 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66477 , H01L21/265 , H01L21/823418 , H01L21/823814 , H01L27/027 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/7833 , H01L29/7835 , H01L29/78612
摘要： An electrostatic discharge (ESD) protection device includes a substrate; a source region of a first conductivity type in the substrate; a drain region of the first conductivity type in the substrate; a gate electrode overlying the substrate between the source region and the drain region; and a core pocket doping region of the second conductivity type within the drain region. The core pocket doping region does not overlap with an edge of the drain region.
摘要翻译：静电放电（ESD）保护装置包括：基板; 在所述衬底中的第一导电类型的源极区; 衬底中的第一导电类型的漏极区域; 在所述源极区域和所述漏极区域之间覆盖所述衬底的栅电极; 以及在漏极区内的第二导电类型的核心袋掺杂区域。核心袋掺杂区域不与漏极区域的边缘重叠。

48. 发明授权

US08779591B2 Bump pad structure 有权
标题翻译：凸块结构
公开(公告)号：US08779591B2
公开(公告)日：2014-07-15
申请号：US13233808
申请日：2011-09-15
申请人： Ming-Tzong Yang , Yu-Hua Huang
发明人： Ming-Tzong Yang , Yu-Hua Huang
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/562 , H01L24/13 , H01L2224/0401 , H01L2224/05011 , H01L2224/05012 , H01L2224/05022 , H01L2224/05088 , H01L2224/05095 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05552 , H01L2224/05558 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2924/00014 , H01L2924/00012
摘要： A bump pad structure for a semiconductor package is disclosed. A bump pad structure includes a conductive pad disposed on an insulating layer. A ring-shaped conductive layer is embedded in the insulating layer and is substantially under and along an edge of the conductive pad. At least one conductive via plug is embedded in the insulating layer and between the conductive pad and the ring-shaped conductive layer, such that the conductive pad is electrically connected to the ring-shaped conductive layer.
摘要翻译：公开了一种用于半导体封装的凸块焊盘结构。凸块焊盘结构包括设置在绝缘层上的导电焊盘。环形导电层嵌入在绝缘层中，并且基本上在导电焊盘的边缘下方并且沿着导电焊盘的边缘。至少一个导电通孔插入绝缘层中，并且在导电垫和环形导电层之间，使得导电垫电连接到环形导电层。

49. 发明申请

US20130037937A1 BUMP PAD STRUCTURE 有权
标题翻译： BUMP PAD结构
公开(公告)号：US20130037937A1
公开(公告)日：2013-02-14
申请号：US13233808
申请日：2011-09-15
申请人： Ming-Tzong Yang , Yu-Hua Huang
发明人： Ming-Tzong Yang , Yu-Hua Huang
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/562 , H01L24/13 , H01L2224/0401 , H01L2224/05011 , H01L2224/05012 , H01L2224/05022 , H01L2224/05088 , H01L2224/05095 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05552 , H01L2224/05558 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2924/00014 , H01L2924/00012
摘要： A bump pad structure for a semiconductor package is disclosed. A bump pad structure includes a conductive pad disposed on an insulating layer. A ring-shaped conductive layer is embedded in the insulating layer and is substantially under and along an edge of the conductive pad. At least one conductive via plug is embedded in the insulating layer and between the conductive pad and the ring-shaped conductive layer, such that the conductive pad is electrically connected to the ring-shaped conductive layer.
摘要翻译：公开了一种用于半导体封装的凸块焊盘结构。凸块焊盘结构包括设置在绝缘层上的导电焊盘。环形导电层嵌入在绝缘层中，并且基本上在导电焊盘的边缘下方并且沿着导电焊盘的边缘。至少一个导电通孔插入绝缘层中，并且在导电垫和环形导电层之间，使得导电垫电连接到环形导电层。

50. 发明授权

US5698349A Sub-resolution phase shift mask 失效
标题翻译：子分辨率相移掩码
公开(公告)号：US5698349A
公开(公告)日：1997-12-16
申请号：US670271
申请日：1996-06-21
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： G03F1/29 , G03F9/00
CPC分类号： G03F1/29
摘要： The invention describes the fabrication and use of a sub-resolution phase shift mask. The mask is formed using a single alignment step with all other alignment steps being accomplished by self alignment. This self alignment is made possible by using vertical anisotropic etching of an opaque material layer to form opaque spacers at the pattern edges of phase shifting material. The opaque spacers combine with phase shifting and other opaque regions of the mask to provide improved image resolution and depth of focus tolerance at the surface of an integrated circuit wafer.
摘要翻译：本发明描述了亚分辨率相移掩模的制造和使用。使用单个对准步骤形成掩模，所有其它对准步骤通过自对准完成。通过使用不透明材料层的垂直各向异性蚀刻在相移材料的图案边缘处形成不透明间隔物，可以实现这种自对准。不透明的间隔物与掩模的相移和其他不透明区域结合，以在集成电路晶片的表面提供改善的图像分辨率和聚焦容限深度。

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