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41. 发明申请

US20060158210A1 METHOD OF PREDICTING HIGH-K SEMICONDUCTOR DEVICE LIFETIME 有权
标题翻译：预测高K半导体器件寿命的方法
公开(公告)号：US20060158210A1
公开(公告)日：2006-07-20
申请号：US11077463
申请日：2005-03-10
申请人： Ching-Wei Tsai , Chih-Hao Wang , Min-Hwa Chi
发明人： Ching-Wei Tsai , Chih-Hao Wang , Min-Hwa Chi
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/2642
摘要： A preferred embodiment of the invention provides a method for testing a MISFET to determine the effect of hot carrier injection (HCI) on integrated circuit lifetime. The method comprises applying a positive stress voltage to a gate having a high-k dielectric, while simultaneously holding a drain voltage equal to the stress voltage. Using a stress voltage that is greater than a normal operating voltage accelerates the degradation and failure of the integrated circuit. Embodiments include monitoring electrical parameters such as threshold voltage, transconductance, linear drain current, or saturation drain current. A pre-selected shift in a monitored electrical parameter indicates device failure. Embodiments include analyzing the data by plotting the logarithm of an accelerated device lifetime versus the gate stress voltage. The device lifetime under operating conditions is predicted by extrapolating the plot for a given device operating voltage.
摘要翻译：本发明的优选实施例提供了一种用于测试MISFET以确定热载流子注入（HCI）对集成电路寿命的影响的方法。该方法包括对具有高k电介质的栅极施加正应力电压，同时保持等于应力电压的漏极电压。使用大于正常工作电压的应力电压可加速集成电路的劣化和故障。实施例包括监测诸如阈值电压，跨导，线性漏极电流或饱和漏极电流之类的电参数。受监控的电气参数中的预选位移表示设备故障。实施例包括通过绘制加速器件寿命与栅极应力电压的对数来分析数据。在运行条件下的器件寿命通过外推给定器件工作电压的曲线来预测。

42. 发明申请

US20050263830A1 Partial replacement silicide gate 有权
标题翻译：局部替代硅化物门
公开(公告)号：US20050263830A1
公开(公告)日：2005-12-01
申请号：US11117153
申请日：2005-04-28
申请人： Chih-Hao Wang , Yen-Ping Wang , Chenming Hu
发明人： Chih-Hao Wang , Yen-Ping Wang , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/49 , H01L29/51 , H01L29/76 , H01L29/786 , H01L29/94 , H01L31/0392 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate dielectric. A dielectric layer is formed over the silicon-containing layer. A top layer is formed over the dielectric layer. The gate dielectric, the silicon-containing layer, the dielectric layer, and the top layer are patterned into a gate stack. A spacer is formed along an edge of the gate stack. The top layer and the dielectric layer are removed. A metal layer is deposited on the silicon-containing layer and silicided.
摘要翻译：提出了一种形成均匀栅极硅化物厚度的完全硅化物栅的方法。在衬底上形成栅极电介质。在栅极电介质上形成含硅层。在含硅层上方形成介电层。在电介质层上形成顶层。栅极电介质，含硅层，电介质层和顶层被图案化成栅叠层。沿栅极堆叠的边缘形成间隔物。去除顶层和介电层。将金属层沉积在含硅层上并硅化。

43. 发明授权

US06531393B2 Salicide integrated solution for embedded virtual-ground memory 有权
公开(公告)号：US06531393B2
公开(公告)日：2003-03-11
申请号：US09760597
申请日：2001-01-16
申请人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang
发明人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang
IPC分类号： H01L2144
CPC分类号： H01L27/112 , H01L21/743 , H01L27/105 , H01L27/11286
摘要： A salicide integrate solution for embedded virtual-ground memory of the present invention provides a controlled distance between poly gates. In this way, the spacers formed on the sidewalls of the poly gates become self fill-upon spacers, and the surface of the substrate is not exposed. Thus, the salicides will not be formed on the surface of the substrate causing the connection of the buried diffusion regions. Moreover, the present invention provides two dummy poly gates located on the outside of the poly gates, so that the buried diffusion regions on the surface of the embedded virtual-ground memory are covered by the poly gates and self fill-up spacer. Utilizing the present invention, the process of forming salicides on the memory cell region and the peripheral logic region can be integrated together.

44. 发明申请

US20130120329A1 DISPLAY PANEL 有权
标题翻译：显示面板
公开(公告)号：US20130120329A1
公开(公告)日：2013-05-16
申请号：US13435043
申请日：2012-03-30
申请人： Chih-Hao Wang , Po-Fu Huang , Chih-Hung Chen
发明人： Chih-Hao Wang , Po-Fu Huang , Chih-Hung Chen
IPC分类号： G09G5/00
CPC分类号： G02F1/13452 , G02F2001/133388 , H01L24/16 , H01L24/29 , H01L2224/131 , H01L2224/16225 , H01L2224/29298 , H01L2224/293 , H01L2224/83385 , H01L2924/07811 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A display panel includes a display area, a non-display area, a plurality of signal pads and a passive covering layer. The non-display area is adjacent to the display area. The signal pads are disposed within the non-display area. The passive covering layer is disposed on the display area and extends to cover at least a portion of the non-display area. The passive covering layer has a first thickness within the display area. The passive covering layer has a second thickness within the non-display area. The first thickness is greater than the second thickness.
摘要翻译：显示面板包括显示区域，非显示区域，多个信号焊盘和无源覆盖层。非显示区域与显示区域相邻。信号垫设置在非显示区域内。被动覆盖层设置在显示区域上并延伸以覆盖非显示区域的至少一部分。被动覆盖层在显示区域内具有第一厚度。无源覆盖层在非显示区域内具有第二厚度。第一厚度大于第二厚度。

45. 发明授权

US07919372B2 Method for forming oxide on ONO structure 有权
标题翻译：在ONO结构上形成氧化物的方法
公开(公告)号：US07919372B2
公开(公告)日：2011-04-05
申请号：US11625177
申请日：2007-01-19
申请人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

46. 发明申请

US20100182278A1 RESISTIVE TOUCH CONTROL DEVICE AND DRIVING METHOD AND DRIVING CONTROLLER THEREOF 失效
标题翻译：电阻式触控控制装置及其驱动方法及驱动控制器
公开(公告)号：US20100182278A1
公开(公告)日：2010-07-22
申请号：US12691741
申请日：2010-01-22
申请人： Jian-Feng Li , Wen-Chun Wang , Chih-Chang Lai , Kuo-Chang Su , Gwo-Sen Lin , Chih-Hao Wang
发明人： Jian-Feng Li , Wen-Chun Wang , Chih-Chang Lai , Kuo-Chang Su , Gwo-Sen Lin , Chih-Hao Wang
IPC分类号： G06F3/045
CPC分类号： G06F3/0416 , G06F3/045 , G06F2203/04104
摘要： A resistive touch control device and driving methods and a driving controller thereof are provided to switch operation modes of a touch panel. Depending on the user's requirement, the touch panel can be operated in multi-touch mode or only in an analog mode with high resolution. In other words, the touch control device can be operated in a digital mode, the analog mode, or a hybrid mode including both of the digital and the analog modes.
摘要翻译：提供电阻式触摸控制装置及其驱动方法及其驱动控制器来切换触摸面板的操作模式。根据用户要求，触摸面板可以在多点触摸模式下操作，也可以仅在具有高分辨率的模拟模式下操作。换句话说，触摸控制装置可以以数字模式，模拟模式或包括数字模式和模拟模式两者的混合模式操作。

47. 发明授权

US07727845B2 Ultra shallow junction formation by solid phase diffusion 有权
标题翻译：通过固相扩散形成超浅结
公开(公告)号：US07727845B2
公开(公告)日：2010-06-01
申请号：US11258469
申请日：2005-10-24
申请人： Chih-Hao Wang , Yen-Ping Wang , Steve Ming Ting , Yi-Chun Huang
发明人： Chih-Hao Wang , Yen-Ping Wang , Steve Ming Ting , Yi-Chun Huang
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/20
CPC分类号： H01L29/6659 , H01L29/165 , H01L29/517 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7833
摘要： An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.
摘要翻译：提供了一种超浅结（USJ）FET器件及其形成方法，其具有改善的对SDE或LDD掺杂区界面的控制以提高器件性能和可靠性，该方法包括提供半导体衬底; 形成栅极结构，所述栅极结构包括栅极电介质，上覆栅极电极和邻近所述栅电极的任一侧的第一偏移间隔物; 在与相应的第一偏移间隔物相邻的相应源极和漏极区域上形成包含掺杂剂的至少一个掺杂半导体层; 在相邻的第一偏移间隔物附近形成第二偏移间隔物; 并且对所述至少一个半导体层进行热处理以引起所述掺杂剂的扩散以在所述半导体衬底中形成掺杂区域。

48. 发明申请

US20080237750A1 Silicided metal gate for multi-threshold voltage configuration 有权
标题翻译：硅化金属栅极，用于多阈值电压配置
公开(公告)号：US20080237750A1
公开(公告)日：2008-10-02
申请号：US11728809
申请日：2007-03-27
申请人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
发明人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L21/28097 , H01L21/82345 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
摘要翻译：具有改进的功函数和良好的DIBL（漏极诱发的势垒降低）和SCE（短沟道效应）特性的低电压阈值MOSFET（MOS场效应晶体管）的PMOS（p沟道金属氧化物半导体）器件，以及一种方法用于制造这样的装置。 PMOS器件包括设置在衬底上并包括硅化栅电极的栅极结构。硅化物优选为富镍，并且包括在栅电极和将栅电极与衬底分离的电介质层之间的界面处或附近的峰值铂浓度。通过多步快速热退火或类似方法制备铂峰区域。 PMOS器件还可以包括两个这样的MOSFET，其中一个是硼掺杂的，其中一个不是。

49. 发明授权

US07323392B2 High performance transistor with a highly stressed channel 有权
标题翻译：具有高应力通道的高性能晶体管
公开(公告)号：US07323392B2
公开(公告)日：2008-01-29
申请号：US11391061
申请日：2006-03-28
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843
摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.
摘要翻译：提供具有高应力沟道区的MOS晶体管及其形成方法。该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层第二半导体板。第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻停止层。在通道区域产生高应力。由于硅化物区域的增加，电流拥挤效应降低。

50. 发明申请

US20070231999A1 High performance transistor with a highly stressed channel 有权
标题翻译：具有高应力通道的高性能晶体管
公开(公告)号：US20070231999A1
公开(公告)日：2007-10-04
申请号：US11391061
申请日：2006-03-28
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843
摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.
摘要翻译：提供具有高应力沟道区的MOS晶体管及其形成方法。该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层第二半导体板。第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻停止层。在通道区域产生高应力。由于硅化物区域的增加，电流拥挤效应降低。

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