专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08358655B2 Computer system and network interface supporting class of service queues 有权
标题翻译：计算机系统和网络接口支持服务队列
公开(公告)号：US08358655B2
公开(公告)日：2013-01-22
申请号：US12757294
申请日：2010-04-09
申请人： Chi-Lie Wang , BaoDong Hu , Scott W. Mitchell
发明人： Chi-Lie Wang , BaoDong Hu , Scott W. Mitchell
IPC分类号： H04L12/28 , H04J3/24
CPC分类号： G06F15/167 , H04L12/40013 , H04L29/0653 , H04L49/90 , H04L49/901 , H04L49/9063
摘要： A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and-outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.
摘要翻译：提供了适用于高速网络通信的数据处理系统，用于管理这种系统的网络接口和网络接口的方法，其中通过网络接收的分组的处理由网络接口层的嵌入式逻辑实现。网络接口上的传入数据包被解析和分类，因为它们存储在缓冲存储器中。耦合到网络接口上的缓冲存储器的功能逻辑能够使用由解析和分类步骤产生的指针和分组分类信息在单个周期内访问分组内的任何数据字段。在数据包从缓冲存储器传出之前，数据包中的数据字段的操作结果是可用的。本发明还提供了一种数据处理系统，网络接口管理方法和网络接口，该系统包括在系统的网络接口层的嵌入式防火墙，可防止内部和外部对安全性的攻击数据处理系统。此外，本发明提供了一种数据处理系统，网络接口管理方法和网络接口，其通过在网络接口级别应用优先级规则来支持从网络进入的分组的服务管理类别系统。

42. 发明授权

US08094677B2 Multi-bus structure for optimizing system performance of a serial buffer 有权
标题翻译：多总线结构，用于优化串行缓冲器的系统性能
公开(公告)号：US08094677B2
公开(公告)日：2012-01-10
申请号：US11679824
申请日：2007-02-27
申请人： Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
发明人： Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
IPC分类号： H04J3/16
CPC分类号： H04L12/4015 , H04L47/10 , H04L47/2441
摘要： A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.
摘要翻译：提供具有解析器和多个并行处理路径的串行缓冲器。解析器接收传入的分组，确定每个分组的类型，然后将每个分组路由到与确定的分组类型相对应的处理路径。分组类型可以包括阻塞优先分组（其实现总线从操作），非阻塞优先分组（其访问串行缓冲器的片上资源）和数据分组（其实现总线主机操作）。由于不同的分组类型在并行处理路径上被处理，所以一种分组类型的处理不会干扰其他分组类型的处理。结果，串行缓冲器内的阻塞条件最小化。

43. 发明授权

US08046614B2 Integrated circuit having a networking interface module supporting a plurality of protocols 有权
标题翻译：具有支持多个协议的网络接口模块的集成电路
公开(公告)号：US08046614B2
公开(公告)日：2011-10-25
申请号：US12505590
申请日：2009-07-20
申请人： Nathan Henderson , Chi-Lie Wang , Baodong Hu
发明人： Nathan Henderson , Chi-Lie Wang , Baodong Hu
IPC分类号： G06F1/32
CPC分类号： G06F1/325 , G06F1/3203 , G06F1/3209 , Y02D30/32 , Y02D50/20
摘要： A computer system comprises host processor and a network interface, wherein the host processor includes resources supporting a full power mode, a lower power mode and a power down mode, as seen in standard system bus specifications such as PCI and InfiniBand. The network interface includes a medium interface unit coupled to network media supporting a least high speed protocol, such as a Gigabit Ethernet or high-speed InfiniBand, and a lower speed protocol, such as one of 10 Mb and 100 Mb Ethernet or a lower speed InfiniBand. Power management circuitry forces the medium interface unit to the lower speed protocol in response to an event signaling entry of the lower power mode. In the lower power mode, the network interface consumes less than the specified power when executing the lower speed protocol, and consumes greater than the specified power when executing the high speed protocol. Logic in the network interface operates in the lower power mode, and uses the lower speed protocol to detect a pattern in incoming packets. In response to the detection of said pattern, the logic issues a reset signal to the host processor. Thus, the network interface operates as a wake-up device in the lower power mode, using the lower speed protocol.
摘要翻译：计算机系统包括主处理器和网络接口，其中主处理器包括支持全功率模式，较低功率模式和掉电模式的资源，如标准系统总线规范（如PCI和InfiniBand）所示。网络接口包括耦合到支持最小高速协议（例如千兆以太网或高速InfiniBand）的网络媒体的介质接口单元和诸如10Mb和100Mb以太网之一或较低速度的低速协议 InfiniBand。响应于较低功率模式的事件信号输入，电源管理电路强制介质接口单元进入低速协议。在较低功率模式下，执行低速协议时，网络接口消耗的功率小于指定功率，在执行高速协议时消耗大于指定功率。网络接口中的逻辑工作在较低功耗模式，并使用较低速度协议来检测输入数据包中的模式。响应于所述模式的检测，逻辑向主处理器发出复位信号。因此，使用较低速度协议，网络接口作为较低功率模式的唤醒设备工作。

44. 发明授权

US07724740B1 Computer system and network interface supporting class of service queues 有权
标题翻译：计算机系统和网络接口支持服务队列
公开(公告)号：US07724740B1
公开(公告)日：2010-05-25
申请号：US10228488
申请日：2002-08-27
申请人： Chi-Lie Wang , BaoDong Hu , Scott W. Mitchell
发明人： Chi-Lie Wang , BaoDong Hu , Scott W. Mitchell
IPC分类号： H04L12/28 , H04J3/24
CPC分类号： G06F15/167 , H04L12/40013 , H04L29/0653 , H04L49/90 , H04L49/901 , H04L49/9063
摘要： A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.
摘要翻译：提供了适用于高速网络通信的数据处理系统，用于管理这种系统的网络接口和网络接口的方法，其中通过网络接收的分组的处理由网络接口层的嵌入式逻辑实现。网络接口上的传入数据包被解析和分类，因为它们存储在缓冲存储器中。耦合到网络接口上的缓冲存储器的功能逻辑能够使用由解析和分类步骤产生的指针和分组分类信息在单个周期内访问分组内的任何数据字段。在数据包从缓冲存储器传出之前，数据包中的数据字段的操作结果是可用的。本发明还提供了一种数据处理系统，网络接口管理方法和网络接口，该系统包括在系统的网络接口层的嵌入式防火墙，可防止内部和外部对数据安全的攻击处理系统。此外，本发明提供了一种数据处理系统，网络接口管理方法和网络接口，其通过在网络接口级别应用优先级规则来支持从网络进入的分组的服务管理类别系统。

45. 发明申请

US20090089532A1 Serial Buffer Supporting Virtual Queue To Physical Memory Mapping 有权
标题翻译：串行缓冲区支持虚拟队列到物理内存映射
公开(公告)号：US20090089532A1
公开(公告)日：2009-04-02
申请号：US11863176
申请日：2007-09-27
申请人： Chi-Lie Wang , Calvin Nguyen , Mario Au
发明人： Chi-Lie Wang , Calvin Nguyen , Mario Au
IPC分类号： G06F13/28
CPC分类号： G06F12/0223 , G06F5/065 , G11C7/1075 , G11C8/12
摘要： A serial buffer having a plurality of virtual queues, which can be allocated to include various combinations of on-chip dual-port memory blocks, on-chip internal memory blocks and/or off-chip external memory blocks. The virtual queues are allocated and accessed in response to configuration bits and size bits stored on the serial buffer. Relatively large external memory blocks can be allocated to virtual queues used for data intensive operations, while relatively small and fast dual-port memory blocks can advantageously be allocated to virtual queues used for passing command and status information. The serial buffer provides an efficient and flexible manner for utilizing available memory, which not only minimizes the access latency but also provides a large amount of buffer space to meet different application needs.
摘要翻译：具有多个虚拟队列的串行缓冲器，其可以被分配以包括片上双端口存储器块，片上内部存储器块和/或片外外部存储器块的各种组合。响应于存储在串行缓冲器上的配置位和大小位，分配和访问虚拟队列。可以将相对较大的外部存储器块分配给用于数据密集型操作的虚拟队列，而相对小且快速的双端口存储器块可以有利地被分配给用于传递命令和状态信息的虚拟队列。串行缓冲器提供了一种有效和灵活的方式来利用可用的存储器，这不仅使访问延迟最小化，而且提供了大量的缓冲空间以满足不同的应用需求。

46. 发明申请

US20080209084A1 Hardware-Based Concurrent Direct Memory Access (DMA) Engines On Serial Rapid Input/Output SRIO Interface 有权
标题翻译：基于硬件的并行直接存储器访问（DMA）引擎串行快速输入/输出SRIO接口
公开(公告)号：US20080209084A1
公开(公告)日：2008-08-28
申请号：US11679820
申请日：2007-02-27
申请人： Chi-Lie Wang , Bertan Tezcan
发明人： Chi-Lie Wang , Bertan Tezcan
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.
摘要翻译：串行缓冲器包括配置为存储从主机接收的数据包的队列。直接存储器访问（DMA）引擎从具有达到相应水印的水位的最高优先级队列接收数据分组。 DMA引擎被配置为响应于从多个DMA寄存器组中选择的DMA寄存器集合。用于配置DMA引擎的DMA寄存器组可以响应于读取的数据分组的头部中的信息，或响应于读取数据分组的队列而被选择。每个DMA寄存器集定义系统存储器中相应的缓冲区，数据包被传输到该缓冲区。每个DMA寄存器集还定义相应的缓冲器是否以卷绕模式或停止模式被访问，以及是否响应于传送到相应缓冲器中的最后地址而生成门铃信号。

47. 发明申请

US20080205438A1 Multi-Bus Structure For Optimizing System Performance Of a Serial Buffer 有权
标题翻译：用于优化串行缓冲器的系统性能的多总线结构
公开(公告)号：US20080205438A1
公开(公告)日：2008-08-28
申请号：US11679824
申请日：2007-02-27
申请人： Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
发明人： Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
IPC分类号： H04J3/22
CPC分类号： H04L12/4015 , H04L47/10 , H04L47/2441
摘要： A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.
摘要翻译：提供具有解析器和多个并行处理路径的串行缓冲器。解析器接收传入的分组，确定每个分组的类型，然后将每个分组路由到与确定的分组类型相对应的处理路径。分组类型可以包括阻塞优先分组（其实现总线从操作），非阻塞优先分组（其访问串行缓冲器的片上资源）和数据分组（其实现总线主机操作）。由于不同的分组类型在并行处理路径上被处理，所以一种分组类型的处理不会干扰其他分组类型的处理。结果，串行缓冲器内的阻塞条件最小化。

48. 发明授权

US07006522B1 System and method for alert generation using network interface 失效
标题翻译：使用网络接口进行警报生成的系统和方法
公开(公告)号：US07006522B1
公开(公告)日：2006-02-28
申请号：US09796063
申请日：2001-02-28
申请人： Chi-Lie Wang , Baodong Hu , Nathan Henderson
发明人： Chi-Lie Wang , Baodong Hu , Nathan Henderson
IPC分类号： H04L12/66
CPC分类号： H04L41/0604
摘要： A system which provides for generation of alert packets using network interfaces. The alert packets are downloaded into a network interface, for example during a transition from an OS-present state to an OS-absent state. The alert packets are provided with control fields which, in various combinations, indicate alert conditions upon which such packets are to be transmitted, and which indicate a repetition mode for transmission of the packet after a match of the alert condition. Logic in the network interface, causes scanning in the plurality of packets downloaded into the network interface at scan intervals to identify packets having control codes matching alert signals received by the network interface. The process allows for more than one alert packet to be matched with a single alert signal during a given scan interval, and to be transmitted. Also, in one embodiment, each alert packet which matches an alert signal can be transmitted according to a repetition mode indicated in the control fields of the packet.
摘要翻译：提供使用网络接口生成警报包的系统。警报包被下载到网络接口中，例如在从OS存在状态到无OS状态的转变期间。报警分组被提供有控制字段，其以各种组合指示要发送这样的分组的警报条件，并且指示用于在警报条件匹配之后传输分组的重复模式。网络接口中的逻辑导致以扫描间隔下载到网络接口中的多个分组中的扫描，以识别具有与网络接口接收的报警信号相匹配的控制码的分组。该过程允许在给定扫描间隔期间将多于一个报警分组与单个警报信号匹配并被发送。此外，在一个实施例中，可以根据分组的控制字段中指示的重复模式来发送与警报信号相匹配的每个警报包。

49. 发明授权

US06970921B1 Network interface supporting virtual paths for quality of service 有权
标题翻译：支持虚拟路径的网络接口，用于服务质量
公开(公告)号：US06970921B1
公开(公告)日：2005-11-29
申请号：US09916377
申请日：2001-07-27
申请人： Chi-Lie Wang , Li-Jau Yang , Kap Soh , Chin-Li Mou
发明人： Chi-Lie Wang , Li-Jau Yang , Kap Soh , Chin-Li Mou
IPC分类号： G06F15/177 , H04L29/06
CPC分类号： H04L47/10 , H04L47/2441 , H04L47/245 , H04L47/50 , H04L47/56 , H04L47/6215 , H04L47/6285 , H04L49/90 , H04L49/901 , H04L63/0272
摘要： A plurality of virtual paths in a network interface between a host port and a network port are managed according to respective priorities. Thus, multiple levels of quality of service are supported through a single physical network port. Variant processes are applied for handling packets which have been downloaded to a network interface, prior to transmission onto the network. The network interface also includes memory used as a transmit buffer, that stores data packets received from the host computer on the first port, and provides data to the second port for transmission on the network. A control circuit in the network interface manages the memory as a plurality of first-in-first-out FIFO queues having respective priorities. Logic places a packet received from the host processor into one of the plurality of FIFO queues according to a quality of service parameter associated with the packets. Logic transmits the packets in the plurality of FIFO queues according to respective priorities. The transmit packet buffer may be statically or dynamically allocated memory.
摘要翻译：在主机端口和网络端口之间的网络接口中的多个虚拟路径根据各自的优先级进行管理。因此，通过单个物理网络端口支持多级服务质量。在传输到网络之前，应用变体过程来处理已经下载到网络接口的分组。网络接口还包括用作发送缓冲器的存储器，其将从主计算机接收的数据分组存储在第一端口上，并且向第二端口提供数据以在网络上传输。网络接口中的控制电路将存储器作为具有各自优先级的多个先进先出FIFO队列进行管理。根据与分组相关联的服务质量参数，逻辑将从主机处理器接收到的分组放置在多个FIFO队列中的一个中。逻辑根据各自的优先级传输多个FIFO队列中的分组。发送分组缓冲器可以是静态或动态分配的存储器。

50. 发明授权

US06760781B1 Intelligent packet transmission engine 有权
标题翻译：智能包传输引擎
公开(公告)号：US06760781B1
公开(公告)日：2004-07-06
申请号：US09505069
申请日：2000-02-16
申请人： Chi-Lie Wang , Ngo Thanh Ho
发明人： Chi-Lie Wang , Ngo Thanh Ho
IPC分类号： G06F1516
CPC分类号： H04L49/9063 , H04L49/90
摘要： Autonomous retransmission of data packets onto a network from a Network Interface Card level upon command from a host processor is support. Efficient FIFO buffering in an ASIC is retained. Uses for autonomous retransmission include hardware and software testing and in network management. One unique process includes: (a) downloading at least one data packet from the host processor to a buffer; (b) storing a parameter indicating a number of retransmissions; (c) transferring packets from the buffer toward the network until all packets of the at least one data packet have been transferred towards the network; and (d) checking a parameter stored on the network interface apparatus, and in response to a particular value of the stored parameter indicating no retransmission, ending the transferring, and in response to other values of the stored parameter, repeating transferring of a last packet in the buffer until the number of retransmissions has been executed or until the host processor commands a cessation of the transferring.
摘要翻译：支持来自主机处理器的命令，从网络接口卡级别自动重传数据包到网络上。保留ASIC中的高效FIFO缓冲。用于自主转发的用途包括硬件和软件测试以及网络管理。一个独特的过程包括：（a）将至少一个数据分组从主机处理器下载到缓冲器;（b）存储指示重传次数的参数;（c）将数据包从缓冲器传送到网络直到所有数据包至少一个数据分组已经被传送到网络; 以及（d）检查存储在所述网络接口装置上的参数，以及响应于所述存储参数的特定值，其指示不重传，结束所述传送，并且响应于所存储参数的其他值，重复传送最后一个分组在缓冲区中直到重新传送的数量已经被执行，或者直到主机处理器命令停止传送。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式